Please choose ALL (multiple answers) correct answers) with explanation. Thank you! Assume register R1 contains an arbitrary integer A, and R2 contains an arbitrary integer B. Which of the following sequences of machine instructions implement the exact condition A < B so that the branch skips the halt instruction? Mark all correct choices. FYI: Be certain; Canvas deducts points for incorrect choices.Option 1:``` 1001 011 001 1 11111 0001 011 011 1 00001 0001 011 010 0 0 011 0000 001 000011111 1111 0000 0010 0101```Option 2:``` 0001 011 001 0 00 010 0000 001 000011111 1111 0000 0010 0101```Option 3:``` 1001 011 001 1 11111 0001 011 011 1 00001 0001 011 010 0 00 011 0000 010 000011111 1111 0000 0010 0101```Option 4:``` 1001 011 010 1 11111 0001 011 011 1 00001 0001 011 001 0 00 011 0000 100 000011111 1111 0000 0010 0101```Option 5:``` 0001 011 001 0 00 010 0000 101 000011111 1111 0000 0010 0101``` **Table of LC-3 Instructions:**| Bits (15 to 0) | Instruction | Semantics ||------------------|-------------|----------------------------------------------------------------------|| **NOT** | 1001 DST SRC 1 1 1 1 1 1 | R[DST] ← NOT(R[SRC]) || **ADD** | 0001 DST SRC1 0 0 0 SRC2 | R[DST] ← R[SRC1] + R[SRC2] || **AND** | 0101 DST SRC1 0 0 0 SRC2 | R[DST] ← R[SRC1] & R[SRC2] || **ADD (Immediate)** | 0001 DST SRC 1 Immediate (5)| R[DST] ← R[SRC] + SEXT(Immediate5) || **AND (Immediate)** | 0101 DST SRC 1 Immediate (5)| R[DST] ← R[SRC] & SEXT(Immediate5) || **LDR** | 0110 DST BASE Offset (6) | R[DST] ← M[R[BASE]+SEXT(Offset6)] || **STR** | 0111 SRC BASE Offset (6) | M[R[BASE]+SEXT(Offset6)] ← R[SRC] || **LD** | 0010 DST PC Offset (9) | R[DST] ← M[inc(PC)+SEXT(PCOffset9)] || **ST** | 0011 SRC PC Offset (9) | M[inc(PC)+SEXT(PCOffset9)] ← R[SRC] || **LDI** | 1010 DST PC Offset (9) | R[DST] ← M[M[inc(PC)+SEXT(PCOffset9)]] || **STI** | 1011 SRC PC Offset (9) | M[M[inc(PC)+SEXT(PCOffset9)]] ← R[SRC] || **LEA** | 1110 DST PC Offset (9) | R[DST] ← inc(PC)+SEXT(PCOffset9) || **BR** | 0000 N Z P PC Offset (9) | PC

Answers: LC3 instructions ADD There are two types of ADD instructions, ADD (Type 1) The result is stored in the destination register after this instruction adds the contents of source registers RS1 and RS2. Syntax: ADD Rd, RS1, RS2 Instruction format 0001 Rd Rs1 0 00 Rs2 ADD (Type 2) This instruction adds the contents of the source registers RS1 to a 5 bit instantaneous value, then stores the result in the destination register. Syntax: ADD Rd, Rs, immediate Instruction format 0001 Rd Rs 1 Immediate BR This instruction checks the condition codes supplied in the instruction and branches to a location found by adding the offset to the program counter if any of the condition codes are set. Syntax: BR offset Instruction format 0000 N Z P Offset N - Negative Z -Zero P - Positive TRAP The system calls input, output, and halt are all carried out via this instruction. The instruction must contain the corresponding 8-bit vector for the service that has to be offered. Syntax: TRAP vector Instruction format 1111 0000 Trapvect8 Trap vector for Halt is 0x25 NOT The source register is supplemented by this instruction, which stores it in the destination. Syntax: NOT Rd, Rs Instruction format, 1001 Rd Rs 1 11111Consider the first instruction sequence: 0001 011 001 0 00 010 0000 010 000011111 1111 0000 0010 0101 So the corresponding instructions are: ADD R3,R1,R2; Add contents of R1 and R2 and store result in R3 BRz x1F; If the result in R3 is 0 then branches to another location TRAP x25; Otherwise halt Therefore, the halt will only be skipped if the sum is 0, but since A=B, this is not possible. Consider the next sequence: 1001 011 001 1 11111 0001 011 011 1 00001 0001 011 010 0 00 011 0000 010 000011111 1111 0000 0010 0101 So the corresponding instructions are: NOT R3,R1 ADD R3,R3,#1 ADD R3,R2,R3 BRz x1F TRAP x25 Here the R1 is complemented and 1 is added, so the 2's complement of the value in R1 is stored in R3, which is actually, -A so when A=B, the addition will be, -A+A =0, so the result of addition will be zero and branch will take place. So this sequence skips halt only if A=B. Consider the next sequence: 1001 011 001 1 11111 0001 011 011 1 00001 0001 011 010 0 00 011 0000 101 000011111 1111 0000 0010 0101 Corresponding instructions are: NOT R3,R1 ADD R3,R3,#1 R3 ADD R3,R3,#1 ADD R3,R2,R3 BRnp x1F BRnp x1F TRAP x25 Here the R1 is complemented and 1 is added, so the 2's complement of the value in R1 is stored in R3, which is actually, -A so when A=B, the addition will be, -A+A =0, so the result of addition will be zero and branch will take place only if the result is non zero, so halt cannot be skipped. Consider the next instruction sequence: 0001 011 001 0 00 010 0000 101 000011111 1111 0000 0010 0101 So the corresponding instructions are: ADD R3,R1,R2 BRnp x1F TRAP x25 So when the sum is not zero the halt will be skipped, but even when A not equal to B, the result will be non-zero, so we cannot assume that A=B even if the halt is skipped. Consider the next instruction sequence: 1001 011 010 1 11111 0001 011 011 1 00001 0001 011 001 0 00 011 0000 010 000011111 1111 0000 0010 0101 Corresponding instructions will be: NOT R3,R2 R3 ADD R3,R3,#1 ADD R3,R1,R3 BRz x1F TRAP x25 Here the R2 is complemented and 1 is added, so the 2's complement of the value in R2 is stored in R3, which is actually, -B so when A=B, the addition will be, -B+B =0, so the result of addition will be zero and branch will take place. So this sequence skips halt only if A=B Consider the next instruction sequence: 1001 011 010 1 11111 0001 011 011 1 00001 0001 011 001 0 00 011 0000 100 000011111 1111 0000 0010 0101 Corresponding instructions will be: NOT R3,R2 R3 ADD R3,R3,#1 ADD R3,R1,R3 R3 BRn x1F TRAP x25 Here the R2 is complemented and 1 is added, so the 2's complement of the value in R2 is stored in R3, which is actually, -B so when A=B, the addition will be, -B+B =0, so the result of addition will be zero and branch will take place only if the result is negative, so halt cannot be skipped. Solution of Table of LC - 3 instruction: Register R1 =xFFFFRegister r2 = x0000 LC-3 instruction: 0001 011 001 0 00 010 ADD DST Src1 Src20001 011 001 000 010 Mode bit = 0, (The mode is registered.) Destination register = R3 source1 register = R1 source2 register = R2 R3 = R1 + R2 R3 = xFFFF + x0000 R3 = xFFFF R3 = 1111 1111 1111 1111 Result is negative, N = 1 Result is Non-zero, Z = 0 p = 1, The parity bit is set to 1 and the bit count is even with a value of 1. No, It is impossible for the LC-3's N and Z condition codes to both be set to 1.