hat counting sequence for which it is desined. Intially the FFs states (AB) were reset to 10.

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Given in the figure is IC 7474 pin configuration. The pin connections of the IC is provided in the Table for the design of a particular counting
sequence. What is that counting sequence for which it is desined. Intially the FFs states (AB) were reset to 10.
D-type Flip-flop Two
Vcc CLR
14U 13
CLK PR
Q
12
11
10
PR
HCLK
CLR
HD
CLR
CLK
PR
CLR D
CLK PR
a GND
D-type Flip-flop One
Table
Signal Value
VCC (Logic 1)
PIN NUMBERS
1, 4, 10, 13 and 14
3 and 11
Connected with a common clock
A
6
A'
7
Ground (Logic 0)
8
B'
9
B
VCC (Logic 1)
Is connected with PIN 8
12
Transcribed Image Text:Given in the figure is IC 7474 pin configuration. The pin connections of the IC is provided in the Table for the design of a particular counting sequence. What is that counting sequence for which it is desined. Intially the FFs states (AB) were reset to 10. D-type Flip-flop Two Vcc CLR 14U 13 CLK PR Q 12 11 10 PR HCLK CLR HD CLR CLK PR CLR D CLK PR a GND D-type Flip-flop One Table Signal Value VCC (Logic 1) PIN NUMBERS 1, 4, 10, 13 and 14 3 and 11 Connected with a common clock A 6 A' 7 Ground (Logic 0) 8 B' 9 B VCC (Logic 1) Is connected with PIN 8 12
O a. (AB): 10 -->11 --> 01
O b. (AB): 10 -->11 --> 10
O c. (AB): 10 --> 00 --> 10
O d. (AB): 10 -->1 --> 10
Transcribed Image Text:O a. (AB): 10 -->11 --> 01 O b. (AB): 10 -->11 --> 10 O c. (AB): 10 --> 00 --> 10 O d. (AB): 10 -->1 --> 10
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