Homework Help is Here – Start Your Trial Now!
Engineering
Computer Engineering
Given the following clock (clk) and input (D) signals, select the correct output values at the labelled times for a positive level sensitive D latch (+ve level D-1), a positive edge triggered D flip-flop (+ve edge D-ff), and a negative edge triggered D flip-flop (-ve edge D-ff). Note: You can assume all memory elements with initial values of 0. clk (a) (b) (c) (d) (e) Input D T₁ T2 T3 T4 At T1, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 1 None of the above

Given the following clock (clk) and input (D) signals, select the correct output values at the labelled times for a positive level sensitive D latch (+ve level D-1), a positive edge triggered D flip-flop (+ve edge D-ff), and a negative edge triggered D flip-flop (-ve edge D-ff). Note: You can assume all memory elements with initial values of 0. clk (a) (b) (c) (d) (e) Input D T₁ T2 T3 T4 At T1, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 1 None of the above

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
See similar textbooks
icon
Related questions
Question

how to answer this question with working, please show working and select the correct option.

Given the following clock (clk) and input (D) signals, select the correct output values at the labelled times for a positive level sensitive D latch (+ve level D-1), a positive edge triggered D flip-flop (+ve edge D-ff), and a negative edge triggered D flip-flop (-ve edge D-ff). Note: You can assume all memory elements with initial values of 0. clk (a) (b) (c) (d) (e) Input D T₁ T2 T3 T4 At T1, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 1 None of the above
Transcribed Image Text:Given the following clock (clk) and input (D) signals, select the correct output values at the labelled times for a positive level sensitive D latch (+ve level D-1), a positive edge triggered D flip-flop (+ve edge D-ff), and a negative edge triggered D flip-flop (-ve edge D-ff). Note: You can assume all memory elements with initial values of 0. clk (a) (b) (c) (d) (e) Input D T₁ T2 T3 T4 At T1, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 1 None of the above
Expert Solution
steps

Step by step

Solved in 2 steps with 3 images

SEE SOLUTIONCheck out a sample Q&A here
Blurred answer
Similar questions
Recommended textbooks for you
Computer Networking: A Top-Down Approach (7th Edi…
Computer Networking: A Top-Down Approach (7th Edi…
Computer Engineering
ISBN:
9780133594140
Author:
James Kurose, Keith Ross
Publisher:
PEARSON
Computer Organization and Design MIPS Edition, Fi…
Computer Organization and Design MIPS Edition, Fi…
Computer Engineering
ISBN:
9780124077263
Author:
David A. Patterson, John L. Hennessy
Publisher:
Elsevier Science
Network+ Guide to Networks (MindTap Course List)
Network+ Guide to Networks (MindTap Course List)
Computer Engineering
ISBN:
9781337569330
Author:
Jill West, Tamara Dean, Jean Andrews
Publisher:
Cengage Learning
Concepts of Database Management
Concepts of Database Management
Computer Engineering
ISBN:
9781337093422
Author:
Joy L. Starks, Philip J. Pratt, Mary Z. Last
Publisher:
Cengage Learning
Prelude to Programming
Prelude to Programming
Computer Engineering
ISBN:
9780133750423
Author:
VENIT, Stewart
Publisher:
Pearson Education
Sc Business Data Communications and Networking, T…
Sc Business Data Communications and Networking, T…
Computer Engineering
ISBN:
9781119368830
Author:
FITZGERALD
Publisher:
WILEY
SEE MORE TEXTBOOKS