Given the following circuit, complete the truth table shown below. Assume the D Flip-Flop is a positive edge-triggered flip-flop. In the truth table, also assume that the given value for D is the value for D at the time the rising edge of the CLK occurs.

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Q: A X D Q Q Q' K Q'

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Q: W Y X Y

A:

Q: F 0 1 1

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