Given the binary assignment table shown blow, complete the design procedure using J-K flip-flop. Present state Input XIX2 Утугуз Next state Output Z X=0X1 000 000 100 1 100 001 011 0 001 000 101 1 101 001 000 0 011 100 101 1

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Q#01: The schematic shown in figure below is for Divide_by_11, a frequency divider, that divides clk by 11 and asserts its output for one cycle. The unit consists of a chain toggle-type flip-flops with additional logic to form an output pulse every 11th pulse of clk. The asynchronous signal rst is active-low and drives Q to 1. Develop and verify a model of Divide_by_11. Vcc 20LSB Q2 03MSB clk clk clk clk clk rst rst rst rst wl w2 clk QB cik_by_11 rst rst

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