Given the binary assignment table shown blow, complete the design procedure using J-K flip-flop. Present state Input XIX2 Утугуз Next state Output Z X=0X1 000 000 100 1 100 001 011 0 001 000 101 1 101 001 000 0 011 100 101 1

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FLIP-FLOPSComplete the timing diagrams for this sequential circuit:

show the waveforms for each flip-flop output with respect For the ring counter in Figure to the clock. Assume that FF0 is initially SET and that the rest are RESET. Show at least ten clock pulses. D D. FFO FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 FP9 CLK

1What will be the state of a MOD64 counter after 90 input pulses if the starting state=000000?A.100100B.011010C.010110D.011100 2.A MOD 32 counter is holding the count 101112. What will the count be after 31 clock pulses?A.10100B.10010C.10000D.10110

need help with digital logic

20. Suppose we have just found yet another representation for floating point numbers. Using this representation, a li2-bit floating point number has 1 bit for the sign of the number, 4 bits for the exponent and 7 bits for the mantissa, which is normalized as in the Simple Model so that the first digit to the right of the radix points must be a 1. Numbers in the exponent are in signed 2's complement representation. No bias is used and there are no implied bits. Show the representation for the smallest positive number this machine can represent using the following format (simply fill in the squares provided). What decimal number does this equate to? : SIGN EXPONENT MANTISSA

Design the following combinational logic circuit with a four-bit input and a three-bit output. The input represents two unsigned 2-bit numbers: A1 A0 and B1 B0. The output C2 C1.C0 is the result of the integer binary division A1 A0/B1 B0 rounded down to three bits. The 3-bit output has a 2-bit unsigned whole part C2 C1 and a fraction part CO. The weight of the fraction bit CO is 21. Note the quotient should be rounded down, i.e. the division 01/11 should give the outputs 00.0 (1/3 rounded down to 0) not 00.1 (1/3 rounded up to 0.5). A result of infinity should be represented as 11.1. A minimal logic implementation is not required. (Hint: start by producing a truth table of your design).

How to build this circuit? (on Digital or Logisim)  Binary-coded decimal is an alternative method of representing integers using binary. In it, each base-10 digit is represented by four bits, thus each nibble takes one of 10 values (0000 through 1001). Therefore, using BCD, 42 (decimal) is represented as 0100 0010 (binary) and 196 (decimal) is represented as 0001 1001 0110 (binary). Create a circuit in Logisim that accepts as input a pair of two-digit integers represented as BCD and outputs their sum in BCD. Any and all Digital components are fair game. You can assume that all inputs will be valid BCD-encoded numbers.

4- Draw the output waveform if the signal shown in Figure below is applied to inputs of J-K Flip-Flop. Q is initially LOW. PR HIGH CLK- K CLR CLK- PR CLR