Given k (a.b.c.d) = Em(0,1,3,4,5,7,9,10,12,14) Implement the function k using only two independent 4:1 MUX's with no additional logic. Inverse of inputs a, b, c, d are available. Show all connections. (Hint: consider rearranging the Kmap in other than abcd order). k. ab ´00 01 11 10 +5V +5V ed 00 01 10 100 01 10 11 00 12 k 01 13 11 10 10

Given k (a.b.c.d) = Em(0,1,3,4,5,7,9,10,12,14) Implement the function k using only two independent 4:1 MUX's with no additional logic. Inverse of inputs a, b, c, d are available. Show all connections. (Hint: consider rearranging the Kmap in other than abcd order). k. ab ´00 01 11 10 +5V +5V ed 00 01 10 100 01 10 11 00 12 k 01 13 11 10 10

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

In the notes on amortized analysis, we gave a “toy example” of a binary counter with the operationscreate and increment. We showed that the amortized times for the create and incement operationswere O(n) and O(1), respectively. To do this, we defined the potential function of the counter to bethe number of 1-bits, counting all bits and not just the rightmost bits.Suppose that instead we were to choose the potential function to be the number of rightmost 1-bits(i.e., the number of 1-bits before the first 0-bit). Show that with this definition of the potentialfunction, the amortized time of the increment operation is not O(1).
Q.2) Consider the Boolean function that we have seen in the class, F(A,B,C,D)= A BC/ + A' CD' + A' B/D'+ A/ C'D a) Implement F using a 4-to-1 MUX, and minimum gates. Connect varaibles B and D to selection inputs S, and S, of the MUX, respectively. b) Implement F using a 4-to-1 MUX, and minimum gates. Connect varaibles A and D to selection inputs S; and S, of the MUX, respectively. c) Implement F using a 4-to-1 MUX, and minimum gates. Connect varaibles A and B to selection inputs S; and S, of the MUX, respectively. d) Implement F using a 4-to-1 MUX, and minimum gates. Connect varaibles C and D to selection inputs S, and S, of the MUX, respectively. For all cases, show the multiplexer implementation tables and draw the circuits. Assume that the complements of the inputs are not available.
5. Consider the following set of Boolean functions: W (p, q, r) = E(1,3, 5,7) X (p, q, r) = E(0,1,5,7) Y (p, q, r) = E(1,3,6) (a) Deduce the optimal ROM truth table for the above functions. (b) Draw the ROM logic diagram to implement the circuit.
1.Consider the following truth table where Z= F(A,B,C). A B 1 1 1 1 1 1 1 1 1 1 1 (a)Show the sum of products representation for Z. (b) Use k-maps to minimize Z directly from the truth table (c)Use a 2-var mux to realize the Z function from the truth table 2.(a) Fill out the truth table for 1-bit full adder below for Sum and Cout A В Cin Sum Cout 1 1 1 1 1 (b)Show a 2-level logic circuit corresponding to sum.(after minimizing) (c)Show a 2-level logic circuit corresponding to Cout.(after minimizing)
2. Consider a unit-energy root-raised-cosine (RRC) pulse which spans over 8 symbol durations. We take 10 samples per symbol (sps) from this RRC pulse. Write an RRC filter function that employs pulse-shaping using the RRC pulse described above. (If there is a single symbol and s=[1 0], the energy of the corresponding length-81 samples vector should be equal to 1.) The parameters of the RRC pulse are roll-off factor, span, and samples per symbol. You should write your pulse-shaping function according to the prototype given below txFilt = myRRCFilter(s, rf, span, sps) where txFilt is the pulse-shaped signal (transmitted signal), s denotes the transmitted symbols, rf is the roll-off factor, span is the span of the filter, and sps is the samples per symbol.
Given a digraph D = (V; A; ') with all but one arc (u; v) having non-negative lengths, explain how to determine if D contains a negative circuit in O (m + n log n) of time.
USE MATLAB TO SOLVE THE PROBLEM A resistor of resistance R is supplied by a battery which consists of voltage source E in series with an internal resistance r. Plot the power P as a function of the resistance R for 1 N
Implement the logic function of Example 7-3 that is shown below using: F (U, V, W, X, Y, Z) = Em (0,4,9,16,20.21,24,30,37,40,42,46,49,52,56,58,62) 1- Four 2*1 MUX & one 4*1 MUX 2- Two 4*1 MUX & one 2*1 MUX
Q2.Simplify the following functions, and implement them with two-level NOR gate circuits: (a) F = wx' + y'z' + w'yz' (b) ) F(w.x.yz) = Σ(0,3, 12, 15) (c) F(xy,2) = [(x + y)(x + z)]'
assuming (47) based 10 = (abcdefg) based 2, consider the Boolean function F (A B C D)given by the followingtruth table for all the questions: a) Implement F( ABCD) using a 8x1 MUX and external gates, choosing inputs A, B, C as the selection inputs of the MUX.b) Implement F( ABCD) using a 8x1 MUX and external gates, choosing inputs B, C, D as the selection inputs of the MUX.c) Implement F( ABCD ) using a 4x1 MUX and external gates, choosing inputs B and C as the selection inputs of the MUX.
Express the following functions as sum of minterms and product of maxterms: (a) F(A, B, C, D) = BD+ AD+ BD (b) F(x, y, z) = (xy +z)(xz + y) %3D
A Boolean function fk of two variables A and B is defined as follows: fk (0, 0) = fk (0, 1) = fk (1, 1) = 1; fk (1, 0) = 0 Assuming complements of A and B are not available, what will be the minimum cost solution for realizing using only 2-input NOR gates and 2-input OR gates (each having unit cost) ? Explain with nessessary digram and expression.