Given circuit The maximum values are determined as, Vos = 25 V Ves = 25 V Small Signal JFET Amplifier Self-biased Circuit VGs-OFF = -4 V Ipss = 30 mA VDD 20V Design Specifications: Av = 9 (gain ratio) Id = 8mA SRD A minimum value of transconductance will be C5 Vout R = 10000 umhos Drain 2.2uF Q2 C4 A, = Gate J309 Vin H 2.2µF Source RG The equation for drain current is obtained as S PRS VDp - IpsRp - Vns - InsRs =0 Ips = Vo-Ve Totks Ve-25 Ips = - sa Applying KVL in drain to source circuit -: info that may be useful on the right VDp - IpRp - Vps - IŞRS = 0 ------ 1) ) Putting value in equation -1) with the help of table (Rp + Rs) = Yan- Vm 20- 10 - 1.25 K2---- 2) %3D Applying KVL in gate to source circuit -: -Vas s - IsRs = 0 Ip = Ves 3) Rs - -* - 4) With the help of the table putting minimum value in equation -4) Rs - - 2- 250 2- s) Putting equation -5) in equation -1)
Given circuit The maximum values are determined as, Vos = 25 V Ves = 25 V Small Signal JFET Amplifier Self-biased Circuit VGs-OFF = -4 V Ipss = 30 mA VDD 20V Design Specifications: Av = 9 (gain ratio) Id = 8mA SRD A minimum value of transconductance will be C5 Vout R = 10000 umhos Drain 2.2uF Q2 C4 A, = Gate J309 Vin H 2.2µF Source RG The equation for drain current is obtained as S PRS VDp - IpsRp - Vns - InsRs =0 Ips = Vo-Ve Totks Ve-25 Ips = - sa Applying KVL in drain to source circuit -: info that may be useful on the right VDp - IpRp - Vps - IŞRS = 0 ------ 1) ) Putting value in equation -1) with the help of table (Rp + Rs) = Yan- Vm 20- 10 - 1.25 K2---- 2) %3D Applying KVL in gate to source circuit -: -Vas s - IsRs = 0 Ip = Ves 3) Rs - -* - 4) With the help of the table putting minimum value in equation -4) Rs - - 2- 250 2- s) Putting equation -5) in equation -1)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
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Transcribed Image Text:Given circuit
The maximum values are determined as,
Vps = 25 V
VGs = 25 V
VGS-OFF = -4 V
Small Signal JFET Amplifier
Self-biased Circuit
VDD 20V
Ipss = 30 mA
Design Specifications:
Av = 9 (gain ratio)
Id = 8mA
3RD
A minimum value of transconductance will be
C5
Vout
8s = 10000 umhos
Drain
Q2
J309
2.2µF
C4
V
A,
=
Gate
Vin
2.2µF
Source
Ins Ro
SRG
The equation for drain current is obtained as,
ERS
20
VDp - IpsRp – Vps - IpsRs = 0
Voo-Vrs
Ips = Rok,
0.8-RD
Ips = V 5
Applying KVL in drain to source circuit -:
info that may be useful
on the right
VDD - IDRD – Vps - IşRs = 0------ 1)
Putting value in equation -1) with the help of table
(Rp + Rs) =
Vrn - Vos
20 – 10 = .25 K2 ---- 2)
Applying KVL in gate to source circuit -:
-VGs - 1sRs = 0
Ip =
3)
Rs =
4)
With the help of the table putting minimum value in equation -4)
Rs -
- - 250 2----5)
Putting equation -5) in equation -1)
Rp = 1.25 KN – 2502

Transcribed Image Text:E. Using a suitable value for RG within the given circuit
Apply a 10mVpPK 10kHz sinewave to the input.
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