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Given an amplifier is designed by cascading self-bias JFET circuit and voltage-divider BJT circuit as shown in Figure 1. The first stage of the amplifier has yos of 50 µS while second stage amplifier has hoe of 20 µS. As a design engineer, you are required to provide the derivation, consideration and assumption that have been taken in your calculation to determine: (a) Overall voltage gain (b) Vo if V, = 2 mV (c) Vioad if a Rioad = 10 kn is connected at the output and the conclusion that can be made as comparison with answer of ii)

Given an amplifier is designed by cascading self-bias JFET circuit and voltage-divider BJT circuit as shown in Figure 1. The first stage of the amplifier has yos of 50 µS while second stage amplifier has hoe of 20 µS. As a design engineer, you are required to provide the derivation, consideration and assumption that have been taken in your calculation to determine: (a) Overall voltage gain (b) Vo if V, = 2 mV (c) Vioad if a Rioad = 10 kn is connected at the output and the conclusion that can be made as comparison with answer of ii)

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
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Given an amplifier is designed by cascading self-bias JFET circuit and voltage-divider BJT circuit as shown in Figure 1. The first stage of the amplifier has yos of 50 µS while second stage amplifier has hoe of 20 µS. As a design engineer, you are required to provide the derivation, consideration and assumption that have been taken in your calculation to determine: (a) Overall voltage gain (b) V, if V; = 2 mV (c) Vioad if a Rioad 10 kN is connected at the output and the conclusion that can be made as comparison with answer of ii) +16V 1.8 k 24 k 2.7 k 0.1uF Fovo 0.05 uF Ioss- 6 mA Beta = 150 Vp=3V 10 M 330 -8.2 k 100uF 22 k2 100uF Figure 1 두
Transcribed Image Text:Given an amplifier is designed by cascading self-bias JFET circuit and voltage-divider BJT circuit as shown in Figure 1. The first stage of the amplifier has yos of 50 µS while second stage amplifier has hoe of 20 µS. As a design engineer, you are required to provide the derivation, consideration and assumption that have been taken in your calculation to determine: (a) Overall voltage gain (b) V, if V; = 2 mV (c) Vioad if a Rioad 10 kN is connected at the output and the conclusion that can be made as comparison with answer of ii) +16V 1.8 k 24 k 2.7 k 0.1uF Fovo 0.05 uF Ioss- 6 mA Beta = 150 Vp=3V 10 M 330 -8.2 k 100uF 22 k2 100uF Figure 1 두
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