Given a CFG, STV TaTb U → Ub | b U V + avc | W WWC | C The equivalent transition diagram description of a PDA with the transition functions (A and B are (A) not shown) is given below. λ, Z, SZ (B) 90 91 92 How many number of transitions are defined on (A) 13 10 5 ☐ None of the correct answer is specified 8

Draw and Simplify using K-map for the expression given below

Asap

Simplify the following expression using K-Maps F(A,B,C,D)=A'BD+AC'D+AB'+BCD+A'C'D

pomts) For EACH of the following NDFSMS, Calculate the value of eps(g) for EACH state q. (1) Show eps(1), eps(2), eps(3), eps(4), eps(5) for & transition. 8, a 3 a.b (2) Show eps(1), eps(2), eps(3), eps(4), eps(5), eps(6), eps(7), eps(8), eps(9), respectively, for ɛ transition. b, ɛ 3 b, ɛ a, E

Our Problem bībo be two-bit binary Let A = a1 ao and B = numbers. A and B can take on values from 0 to 3 (for example, A = 2 when aj ao = 10. Let C be a two bit binary number whose value equals the magnitude of the difference A – B. We have C = c¡c0 = |A – B|. (This means that if B is larger than A then you consider B-A.) You are to design a circuit which accepts A and B (i.e., aj aob¡bo) as inputs and outputs the result C = c¡c0. The circuit thus has four inputs and two outputs. For example, the circuit should output cjco = 10 when ajao = 01 and bibo = 11 (C = 2 when A = 1 and B = 3). -

Let L1 = {w | w contains any number of 0s and exactly one 1} and L2 = {w | w starts with 0 or ends with 0}. Draw the state transition diagrams for the DFAs and write the formal 5-tuple definitions for it. Let L3 = L1 ∪ L2 , design the DFA that recognizes L3, show every step of your construction according to the procedure specified on the text book for the regular operation union, and finally draw the state transition diagram.

K85

What is the LUT mask for an FPGA that is implementing F = E(1, 3, 7, 13)?

DRAW STATE DIAGRAM