Given a 4-bit signed integer, design a circuit that outputs its absolute value. You can assume that the input will always have a valid output. (a) Draw a logic diagram of this circuit. You may use 4-bit half adder(s), 2x1 4-bit multiplexer(s), and any logic gate(s) in your design. (b) With the following Verilog code, implement your design above in Verilog. module half_adder (input [3:0] a, input [3:0] b, output [3:0] s); assign s = a + b; endmodule module mux(input [3:0] D0, input [3:0] D1, input S, output reg [3:0] O); always @(*) begin if (S == 0) O = D0; else if (S == 1) O = D1; else O = 4’bx; end

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