For VA = VB = 0V and neglecting all base currents, design the circuit so that each of Q1 and Q2 operates at a dc bias current of 0.4 mA, VC = VD = +10V, VE = 0V, and Q5 operates at a dc bias current of 1.8 mA. Specify the dc bias current at which each of Q3 and Q4
For VA = VB = 0V and neglecting all base currents, design the circuit so that each of Q1 and Q2 operates at a dc bias current of 0.4 mA, VC = VD = +10V, VE = 0V, and Q5 operates at a dc bias current of 1.8 mA. Specify the dc bias current at which each of Q3 and Q4
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Refer to the Image Attached. Neglect the Early effect (that is, assume ro = ∞) and assume |VBE| = 0.7V.
- For VA = VB = 0V and neglecting all base currents, design the circuit so that each of Q1 and Q2 operates at a dc bias current of 0.4 mA, VC = VD = +10V, VE = 0V, and Q5 operates at a dc bias current of 1.8 mA. Specify the dc bias current at which each of Q3 and Q4 will be operating and give the required values of R1, R2, R3, R4, and R5.
- If β = 100, what must the value of each of the two resistances labeled Re be to obtain an input differential resistance of 54 kΩ?
- Find the differential voltage gain of the input stage, Q1−Q2.
- Find the voltage gain of the second stage, Q3−Q4.
- Find the voltage gain of the output stage, Q5.
- Find the overall voltage gain, vout/vid, where vout is the ac output voltage at node E, and vid is the differential input between the bases of Q1 and Q2.
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