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For a nc operatic cycles v clock cy Relative

For a nc operatic cycles v clock cy Relative

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Consider a 5-stage pipeline with the following features: • The pipeline clock rate is 1 GHz • For a non-pipelined implementation, ALU operations and branches take 3 clock cycles while memory operation will take 5 clock cycles. • Relative frequencies of ALU operations, branches, and memory operations are 50%, 30%, 20%. • In the pipeline due to clock setup time, the clock cycle time increases by 0.65ns. Calculate the estimated speed up.
Transcribed Image Text:Consider a 5-stage pipeline with the following features: • The pipeline clock rate is 1 GHz • For a non-pipelined implementation, ALU operations and branches take 3 clock cycles while memory operation will take 5 clock cycles. • Relative frequencies of ALU operations, branches, and memory operations are 50%, 30%, 20%. • In the pipeline due to clock setup time, the clock cycle time increases by 0.65ns. Calculate the estimated speed up.
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