Table 6-43 Truth table for a 74x157 2-input, 4-bit multiplexer. Outputs Inputs EN_L S 1Y 2Y 3Y 4Y х 2DO 3DO 4DO 1DO 101 3D1 4D1 201 Figure 6-61 The 74x157 2-input, 4-bit multiplexer: (a) logic diagram; (b) traditional logic symbol. (15) (b) 74x157 EN_L (1) 15 EN 1D0 1D1 2D0 (2) 2Y 2D1 11 3D0 10 3D1 14 4D0 13 4D1 (4) 3Y 1Y (3) 1D1 12 (5) 2Y (6) 201 (11) 3D0 (9) 3Y (10) 3D1 (14) (12) 4Y (13) 4D1
Using the 74x157, a 2-input 4-bit multiplexer. Study its logic diagram (Figure 6-61) and truth table (Table 6-43). And design a 3-input, 5-bit multiplexer. The three data sources are (D04, D03, D02, D01, D00), (D14, D13, D12, D11, D10) and (D24, D23, D22, D21, D20), respectively. The selection bits are (S1, S0). The outputs are (Y4, Y3, Y2, Y1, Y0). No enable bit is needed. No active-low logic required. All outputs are zero when (S1, S0) = (1,1).
(1) Write the truth table of the multiplexer;
(2) Draw a logic diagram of the multiplexer.
Note: In your truth table and logic diagram, all input/output signals and logic symbols need to be clearly and correctly labeled.
![Table 6-43
Truth table for a
74x157 2-input,
4-bit multiplexer.
Outputs
Inputs
EN_L S
1Y
2Y
3Y
4Y
х
2DO
3DO
4DO
1DO
101
3D1
4D1
201](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Feeb4316e-6c70-4ea3-a169-6f66e4923867%2F67818ef3-e0a2-4aaa-8916-04e4c3b0f5d9%2Ftcdh2n.png&w=3840&q=75)
![Figure 6-61 The 74x157 2-input, 4-bit multiplexer: (a) logic diagram;
(b) traditional logic symbol.
(15)
(b)
74x157
EN_L
(1)
15
EN
1D0
1D1
2D0
(2)
2Y
2D1
11
3D0
10
3D1
14
4D0
13
4D1
(4)
3Y
1Y
(3)
1D1
12
(5)
2Y
(6)
201
(11)
3D0
(9)
3Y
(10)
3D1
(14)
(12)
4Y
(13)
4D1](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Feeb4316e-6c70-4ea3-a169-6f66e4923867%2F67818ef3-e0a2-4aaa-8916-04e4c3b0f5d9%2Fut0fb1.png&w=3840&q=75)
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