Fetch Decode Indirect Interrupt: R'To: AR PC R'T: IR M[AR], PC PC + 1 R'T2: Do, D, Decode IR(12-14), AR IR(0-11), I+IR(15) AR-M[AR] D'½IT 3: R 1 TOTT (IEN)(FGI + FGO): M[AR] TR, PC+0 PC PC+1, IEN 0, R←0, SC-0 DR-M[AR] AC ACA DR, SC+0 DR-M[AR] AC AC DR, E+Coul, SC+0 DR-M[AR] RTo: AR 0, TR PC RT₁: RT 2: Memory-reference: AND DOT 4: DoTs: ADD ᎠᎢ ; DITS: LDA D₂T 4: D₂Ts: STA D3T 4: BUN DATA: BSA DST 4 DsTs: ISZ D6T4 DoTs: ᎠᎢ ; Register-reference: AC DR, SC 0 M[AR] AC, SC-0 PC AR, SC 0 M[AR] PC, AR AR + 1 PC AR, SC 0 DR-M[AR] DR DR+1 M[AR] DR, if (DR = 0) then (PC + PC + 1), SC+0 D₁I'Tr(common to all register-reference instructions) IR(i) = B, (i = 0, 1, 2, ..., 11) r: SC 0 CLA TB11: AC 0 CLE rB 10: E 0 CMA rB9: AC AC CME rBB: E-E CIR rB7: AC shr AC, AC(15) -E, E-AC(0) CIL гB6: AC shl AC, AC(0)-E, E-AC(15) INC rBs: AC AC +1 SPA rB₁: SNA rB3: SZA rB₂: SZE TB₁: HLT rBo: Input-output: - If (AC(15) = 0) then (PC PC +1) If (AC(15) = 1) then (PC PC + 1) If (AC = 0) then PC PC + 1) If (E 0) then (PC + PC + 1) S+O D₁IT=p (common to all input-output instructions) IR(i) = B. (i = 6, 7, 8, 9, 10, 11) SC 0 AC(0-7) INPR, FGI-0 OUTR―AC(0–7), FGO-0 p: INP OUT PB11: PB10: SKI PB9: If (FGI = 1) then (PC PC + 1) SKO PBB: = If (FGO 1) then (PC PC + 1) ION PB7: IEN 1 IOF PB6: IEN 0
Fetch Decode Indirect Interrupt: R'To: AR PC R'T: IR M[AR], PC PC + 1 R'T2: Do, D, Decode IR(12-14), AR IR(0-11), I+IR(15) AR-M[AR] D'½IT 3: R 1 TOTT (IEN)(FGI + FGO): M[AR] TR, PC+0 PC PC+1, IEN 0, R←0, SC-0 DR-M[AR] AC ACA DR, SC+0 DR-M[AR] AC AC DR, E+Coul, SC+0 DR-M[AR] RTo: AR 0, TR PC RT₁: RT 2: Memory-reference: AND DOT 4: DoTs: ADD ᎠᎢ ; DITS: LDA D₂T 4: D₂Ts: STA D3T 4: BUN DATA: BSA DST 4 DsTs: ISZ D6T4 DoTs: ᎠᎢ ; Register-reference: AC DR, SC 0 M[AR] AC, SC-0 PC AR, SC 0 M[AR] PC, AR AR + 1 PC AR, SC 0 DR-M[AR] DR DR+1 M[AR] DR, if (DR = 0) then (PC + PC + 1), SC+0 D₁I'Tr(common to all register-reference instructions) IR(i) = B, (i = 0, 1, 2, ..., 11) r: SC 0 CLA TB11: AC 0 CLE rB 10: E 0 CMA rB9: AC AC CME rBB: E-E CIR rB7: AC shr AC, AC(15) -E, E-AC(0) CIL гB6: AC shl AC, AC(0)-E, E-AC(15) INC rBs: AC AC +1 SPA rB₁: SNA rB3: SZA rB₂: SZE TB₁: HLT rBo: Input-output: - If (AC(15) = 0) then (PC PC +1) If (AC(15) = 1) then (PC PC + 1) If (AC = 0) then PC PC + 1) If (E 0) then (PC + PC + 1) S+O D₁IT=p (common to all input-output instructions) IR(i) = B. (i = 6, 7, 8, 9, 10, 11) SC 0 AC(0-7) INPR, FGI-0 OUTR―AC(0–7), FGO-0 p: INP OUT PB11: PB10: SKI PB9: If (FGI = 1) then (PC PC + 1) SKO PBB: = If (FGO 1) then (PC PC + 1) ION PB7: IEN 1 IOF PB6: IEN 0
Chapter8: Data And Network Communication Technology
Section: Chapter Questions
Problem 41VE
Related questions
Question
computer architecture and organization
according to bilow table picture
how to find the equivalent machine codes of the basic computer whose command format is given bilow based on bilow table picture
2A25
1A26
7040
4A27
7001
![Fetch
Decode
Indirect
Interrupt:
R'To: AR PC
R'T: IR M[AR], PC PC + 1
R'T2: Do, D, Decode IR(12-14),
AR IR(0-11), I+IR(15)
AR-M[AR]
D'½IT 3:
R 1
TOTT (IEN)(FGI + FGO):
M[AR] TR, PC+0
PC PC+1, IEN 0, R←0, SC-0
DR-M[AR]
AC ACA DR, SC+0
DR-M[AR]
AC AC DR, E+Coul, SC+0
DR-M[AR]
RTo:
AR 0, TR PC
RT₁:
RT 2:
Memory-reference:
AND
DOT 4:
DoTs:
ADD
ᎠᎢ ;
DITS:
LDA
D₂T 4:
D₂Ts:
STA
D3T 4:
BUN
DATA:
BSA
DST 4
DsTs:
ISZ
D6T4
DoTs:
ᎠᎢ ;
Register-reference:
AC DR, SC 0
M[AR] AC, SC-0
PC AR, SC 0
M[AR] PC, AR AR + 1
PC AR, SC 0
DR-M[AR]
DR DR+1
M[AR] DR, if (DR = 0) then (PC + PC + 1), SC+0
D₁I'Tr(common to all register-reference instructions)
IR(i) = B, (i = 0, 1, 2, ..., 11)
r: SC 0
CLA
TB11:
AC 0
CLE
rB 10:
E 0
CMA
rB9:
AC AC
CME
rBB:
E-E
CIR
rB7:
AC shr AC,
AC(15) -E, E-AC(0)
CIL
гB6:
AC
shl AC,
AC(0)-E, E-AC(15)
INC
rBs:
AC AC +1
SPA
rB₁:
SNA
rB3:
SZA
rB₂:
SZE
TB₁:
HLT
rBo:
Input-output:
-
If (AC(15) = 0) then (PC PC +1)
If (AC(15) = 1) then (PC PC + 1)
If (AC
=
0) then PC PC + 1)
If (E 0) then (PC + PC + 1)
S+O
D₁IT=p (common to all input-output instructions)
IR(i) = B. (i = 6, 7, 8, 9, 10, 11)
SC 0
AC(0-7) INPR, FGI-0
OUTR―AC(0–7), FGO-0
p:
INP
OUT
PB11:
PB10:
SKI
PB9:
If (FGI = 1) then (PC
PC + 1)
SKO
PBB:
=
If (FGO 1) then (PC
PC + 1)
ION
PB7:
IEN
1
IOF
PB6:
IEN 0](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F2cd79f82-3730-49d1-8559-a01cc4e6e9ca%2F2e103aa7-be66-4a2b-8646-88eb10803c21%2Fan8y5dm_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Fetch
Decode
Indirect
Interrupt:
R'To: AR PC
R'T: IR M[AR], PC PC + 1
R'T2: Do, D, Decode IR(12-14),
AR IR(0-11), I+IR(15)
AR-M[AR]
D'½IT 3:
R 1
TOTT (IEN)(FGI + FGO):
M[AR] TR, PC+0
PC PC+1, IEN 0, R←0, SC-0
DR-M[AR]
AC ACA DR, SC+0
DR-M[AR]
AC AC DR, E+Coul, SC+0
DR-M[AR]
RTo:
AR 0, TR PC
RT₁:
RT 2:
Memory-reference:
AND
DOT 4:
DoTs:
ADD
ᎠᎢ ;
DITS:
LDA
D₂T 4:
D₂Ts:
STA
D3T 4:
BUN
DATA:
BSA
DST 4
DsTs:
ISZ
D6T4
DoTs:
ᎠᎢ ;
Register-reference:
AC DR, SC 0
M[AR] AC, SC-0
PC AR, SC 0
M[AR] PC, AR AR + 1
PC AR, SC 0
DR-M[AR]
DR DR+1
M[AR] DR, if (DR = 0) then (PC + PC + 1), SC+0
D₁I'Tr(common to all register-reference instructions)
IR(i) = B, (i = 0, 1, 2, ..., 11)
r: SC 0
CLA
TB11:
AC 0
CLE
rB 10:
E 0
CMA
rB9:
AC AC
CME
rBB:
E-E
CIR
rB7:
AC shr AC,
AC(15) -E, E-AC(0)
CIL
гB6:
AC
shl AC,
AC(0)-E, E-AC(15)
INC
rBs:
AC AC +1
SPA
rB₁:
SNA
rB3:
SZA
rB₂:
SZE
TB₁:
HLT
rBo:
Input-output:
-
If (AC(15) = 0) then (PC PC +1)
If (AC(15) = 1) then (PC PC + 1)
If (AC
=
0) then PC PC + 1)
If (E 0) then (PC + PC + 1)
S+O
D₁IT=p (common to all input-output instructions)
IR(i) = B. (i = 6, 7, 8, 9, 10, 11)
SC 0
AC(0-7) INPR, FGI-0
OUTR―AC(0–7), FGO-0
p:
INP
OUT
PB11:
PB10:
SKI
PB9:
If (FGI = 1) then (PC
PC + 1)
SKO
PBB:
=
If (FGO 1) then (PC
PC + 1)
ION
PB7:
IEN
1
IOF
PB6:
IEN 0
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