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- 1- Write the VHDL code for the circuit shown in figure2. The circuit acts as support circuit for the control unit. It takes 5 bit from a 7 bit bus and start counting down at the rising Bus edge of each clock cycle in case the "Decr" signal is active. A new data loaded to the (4.0) n shift count 5-bit down counter CLK Decr circuit each time the "Ld" signal activated. The output "n" is equal to "1" in case the count value reaches "00000". Explain why the control unit Ld n 04.00 n-0 needs such circuit. Do functional simulation for your design. Figure 21. design an 8 bit common bus based circuit that supports addition of two 8 bit values. There are two data registers: RegA and RegB. The adder needs to be accumulator based; this means that one operand must be found in the accumulator register, AC, and the other will be loaded from the common bus. The circuit must support AC + RegA as well as AC + RegB. 2. For example, suppose you want to add RegA + RegB. If RegA contains 1216 and RegB contains 3416, you must manipulate the circuit through control signals so that the adder can add up the AC + a register operand. You may use Adder-8 from the parts library. The sum from the adder must be loaded back into the AC. 3. The circuit must be able to move data on the bus from one register to the AC or to the adder. There are no point-to-point connections between components; however, the AC can load data either from the bus or from the output sum of the adder. You will need to include a mux to control that capability. 4. Each register, RegA,…Create a circuit using Logism that implements a memory register capable of storing a 4-bit binary number. You should investigate the different circuits that can be used to store a bit of memory and then utilize the one that meets the following requirements. Your register circuit must be able to support the inputs detailed in the ATTACHED diagram. Each bit of the register circuit must support a data in, a data out, and a control. The control functions such that the data value will only be changed when the control bit is toggled on. The value in the register must be persistent and can only be changed when the control bit has been toggled. You should develop and test the 4-bit register using logism. When you have successfully developed a functioning 4-bit register, you should duplicate the circuit and add it to the two inputs of the ALU circuit that you developed in the previous unit. Complete and test all of your circuits using Logism.
- II. IMPLEMENTATION OF SIMPLE SYSTEMS. Implement the given RTL below using bus connection and multiplexers and/or tri-state buffers. Assume that the given control signals are all mutually exclusive, and all registers are 4-bit wide. You may include additional flip-flop pins if necessary. A: W + Z,V + 1(high) B: X + V,Z + V C: X +W,Y + 0 (low) D: V + Y,W + Y,z-Y E: Y + X,Z + XCreate a circuit using Logism that implements a memory register capable of storing a 4-bit binary number. You should investigate the different circuits that can be used to store a bit of memory and then utilize the one that meets the following requirements. Your register circuit must be able to support the inputs detailed in the following diagram: CHECK ATTACHMENT PLEASE Each bit of the register circuit must support a data in, a data out, and a control. The control functions such that the data value will only be changed when the control bit is toggled on. The value in the register must be persistent and can only be changed when the control bit has been toggled. Develop and test the 4 bit register using logism. When you have successfully developed a functioning 4 bit register, you should duplicate the circuit and add it to the two inputs of the ALU circuit that I ATTACHED.(png format ) You can covert to .circ file to work with.Given 8 registers of 3 bit each. Design a bus using 2 to 4 line decoders and tri state buffers and explain its working with the help of truth table.
- I want the Verilog Code (including test bench code) of the Moore/Mealy Machine. Please elaborate it by more than 2 methods each. CLK -> 1Hz Input : in -> Bus SW8 Output : out -> LED1 state_out[0] ~ state_out[3] -> LED9 ~ LED12Write a Verilog HDL of an eight-bit arithmetic logic unit (ALU). The circuit has a three-bit select bus (Sel), two sixteen-bit input datapaths, an eight-bit output (y) datapath and performs the arithmetic and logic operations listed below. Verify using a testbench.As you know that transferring information among registers in any multiple register configuration is a common bus system. So, explain this register transfer through bus system in which it has to be constructed with three-state gates instead of multiplexers...?
- (b) Draw the transistor level circuit diagram of a 2X2 bit six transistor static RAM cell array. Clearly show the row select and column select signal in your circuit. Explain the write operaion and the read operation of the memory cell assuming a “1” being stored and then read to the 1st row, 2nd coloumn of the array.a) Why do Boolean functions play a central role in hardware architectures? b) Describe Composite Gates. c) Describe Multiplexors and Demultiplexors? What is the importance of the use of the selection bit and the data bits?Describe the SBB instruction in further detail.