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EXPERIMEN Combinational Logic Circuit Design Objectives • To gain experience in combinational logic minimization using the K-map method.

EXPERIMEN Combinational Logic Circuit Design Objectives • To gain experience in combinational logic minimization using the K-map method.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
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EXPERIMENT 2: Combinational Logic Circuit Design Objectives • To gain experience in combinational logic minimization using the K-map method. • To design and construct and verify a 2-bit combinational multiplier. • To gain further experience in connecting digital logic circuits using a breadboard. Introduction The fastest possible implementation of combinational logic is always given by a two-level stan- dard form (sum-of-products or product of sums). In this experiment, a 2-bit combinational logic multiplier circuit will be designed an tested. The multiplier has two 2-bit binary input (A¡A, and B,Bo) and a 4-bit output (P3P2P¡Po). Note the use of the subscript notation to differentiate the bits of the inputs and output with the most significant bit labelled with subscript 1 and 3 respec- tivey. For example, 3 multiplied by 2 in binary would performed using the 'grade school' shift and add method as: 11 10 00 (0 multiplied by 11 = 00) + 110 0110 (shift a 0, 1 multiplied by 11 = 11) The truth table for the binary multiplier with inputs A¡A, and B,B, and output P3P,P¡Po with the subscript 1 and 3 used for the most significant bit of the input and output respectively is given in Table 1: Table 1: Truth table for binary multiplier (inputs A1A9, B¡B0, and outputs P3P2P¡Po) Output value in A1 Ao BỊ Bo P3 P2 P1 Ро decimal 1 1 1 1 1 1 1 1 1 2
Transcribed Image Text:EXPERIMENT 2: Combinational Logic Circuit Design Objectives • To gain experience in combinational logic minimization using the K-map method. • To design and construct and verify a 2-bit combinational multiplier. • To gain further experience in connecting digital logic circuits using a breadboard. Introduction The fastest possible implementation of combinational logic is always given by a two-level stan- dard form (sum-of-products or product of sums). In this experiment, a 2-bit combinational logic multiplier circuit will be designed an tested. The multiplier has two 2-bit binary input (A¡A, and B,Bo) and a 4-bit output (P3P2P¡Po). Note the use of the subscript notation to differentiate the bits of the inputs and output with the most significant bit labelled with subscript 1 and 3 respec- tivey. For example, 3 multiplied by 2 in binary would performed using the 'grade school' shift and add method as: 11 10 00 (0 multiplied by 11 = 00) + 110 0110 (shift a 0, 1 multiplied by 11 = 11) The truth table for the binary multiplier with inputs A¡A, and B,B, and output P3P,P¡Po with the subscript 1 and 3 used for the most significant bit of the input and output respectively is given in Table 1: Table 1: Truth table for binary multiplier (inputs A1A9, B¡B0, and outputs P3P2P¡Po) Output value in A1 Ao BỊ Bo P3 P2 P1 Ро decimal 1 1 1 1 1 1 1 1 1 2
Table 1: Truth table for binary multiplier (inputs A¡A9, B¡Bo, and outputs P3P2P¡Po) Output value in decimal A1 Ao BỊ Bo P3 P2 P1 Ро |0 1 1 1 1 1 3 1 1 1 1 2 1 1 1 6 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 1 9. Questions 1) How many rows would the truth table of a combinational 3-bit multiplier have? How many outputs would be required? What kind of a K-map would be required to minimize this truth table? 2) Obtain the minimal sum-of-product Boolean expression for the truth table of the circuit in Figure 1.7 of Experiment 1. Comment on the circuit provided in Figure 1.8 of Experiment 1 and its relationship with the obtained minimal sum-of-products expression. 3) Design the 2-bit multiplier using the truth table and four 4-variable K-maps. Obtain the standard sum-of-products expression for each output. 4) Draw the schematic diagram of the multiplier circuit taking care to label each gate with its part number, instance number, and pin numbers. Conclusions State what was achieved in the lab and contrast with the experiment objectives. Conclude on the salient portions of the lab. 6.
Transcribed Image Text:Table 1: Truth table for binary multiplier (inputs A¡A9, B¡Bo, and outputs P3P2P¡Po) Output value in decimal A1 Ao BỊ Bo P3 P2 P1 Ро |0 1 1 1 1 1 3 1 1 1 1 2 1 1 1 6 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 1 9. Questions 1) How many rows would the truth table of a combinational 3-bit multiplier have? How many outputs would be required? What kind of a K-map would be required to minimize this truth table? 2) Obtain the minimal sum-of-product Boolean expression for the truth table of the circuit in Figure 1.7 of Experiment 1. Comment on the circuit provided in Figure 1.8 of Experiment 1 and its relationship with the obtained minimal sum-of-products expression. 3) Design the 2-bit multiplier using the truth table and four 4-variable K-maps. Obtain the standard sum-of-products expression for each output. 4) Draw the schematic diagram of the multiplier circuit taking care to label each gate with its part number, instance number, and pin numbers. Conclusions State what was achieved in the lab and contrast with the experiment objectives. Conclude on the salient portions of the lab. 6.
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