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EXERCISE: Draw a four-input NAND gate similar to the five-input gate in Fig. 7.25. What are the W/L ratios of the transistors?

EXERCISE: Draw a four-input NAND gate similar to the five-input gate in Fig. 7.25. What are the W/L ratios of the transistors?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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TABLE 7.6 CMOS NAND Gate Truth Table and Transistor States B Y = AB NMOS-A NMOS-B PMOS-A PMOS-B 1 Off Off On On 1 1 Off On On Off 1 On Off Off On 1 1 On On Off Off The Multi-Input NAND Gate As another example, the circuit for a five-input NAND gate is given in Fig. 7.25. The NMOS network consists of a series stack of five transistors with one MOS device for each input variable. The PMOS network consists of a group of PMOS devices in parallel, also with one transistor for each input. To maintain the speed on the high-to-low transition in the five-input gate, the NMOS transistors must each be five times larger than that of the reference inverter, whereas the PMOS transistors are each identical to that of the reference inverter. EXERCISE: Draw a four-input NAND gate similar to the five-input gate in Fig. 7.25. What are the W/L ratios of the transistors? ANSWERS: 8/1; 5/1
Transcribed Image Text:TABLE 7.6 CMOS NAND Gate Truth Table and Transistor States B Y = AB NMOS-A NMOS-B PMOS-A PMOS-B 1 Off Off On On 1 1 Off On On Off 1 On Off Off On 1 1 On On Off Off The Multi-Input NAND Gate As another example, the circuit for a five-input NAND gate is given in Fig. 7.25. The NMOS network consists of a series stack of five transistors with one MOS device for each input variable. The PMOS network consists of a group of PMOS devices in parallel, also with one transistor for each input. To maintain the speed on the high-to-low transition in the five-input gate, the NMOS transistors must each be five times larger than that of the reference inverter, whereas the PMOS transistors are each identical to that of the reference inverter. EXERCISE: Draw a four-input NAND gate similar to the five-input gate in Fig. 7.25. What are the W/L ratios of the transistors? ANSWERS: 8/1; 5/1
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