Exercise 7. A bit-stream converter is a simple circuit that reads a sequence of bits, one at a time, and outputs another sequence of bits depending on its specification. Consider the following FSM diagram, it implements a bit-stream converter with the specification: • 00 → 01 . 0101 . 10 10 1110 B 1/1 0/0 A 0/0 0/1 1/0 1/1 (a) Create a truth table which encodes this FSM. (Hint: encode each state A,B,C using some unique binary number). (b) For each output in your truth table from part (a), give its disjunctive normal form. (Hint: handle each bit of the binary number encoding the state separately).

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
Question

Computer science 

Exercise 7. A bit-stream converter is a simple circuit that reads a sequence of bits, one
at a time, and outputs another sequence of bits depending on its specification. Consider the
following FSM diagram, it implements a bit-stream converter with the specification:
. 00 → 01
. 01 01
• 10 → 10
• 11 → 10
B
1/1
0/0
A
0/0
0/1
1/0
1/1
(a)
Create a truth table which encodes this FSM. (Hint: encode each state
A,B,C using some unique binary number).
(b)
For each output in your truth table from part (a), give its disjunctive normal
form. (Hint: handle each bit of the binary number encoding the state separately).
(c)
Draw the combinational logic circuit implementing this FSM. That is, you
do not need to show the registers or feedback loop, only the circuit encoding the logic. Use
only gates with an arity of 2. (Hint: this circuit should have 3 inputs and 3 outputs).
Transcribed Image Text:Exercise 7. A bit-stream converter is a simple circuit that reads a sequence of bits, one at a time, and outputs another sequence of bits depending on its specification. Consider the following FSM diagram, it implements a bit-stream converter with the specification: . 00 → 01 . 01 01 • 10 → 10 • 11 → 10 B 1/1 0/0 A 0/0 0/1 1/0 1/1 (a) Create a truth table which encodes this FSM. (Hint: encode each state A,B,C using some unique binary number). (b) For each output in your truth table from part (a), give its disjunctive normal form. (Hint: handle each bit of the binary number encoding the state separately). (c) Draw the combinational logic circuit implementing this FSM. That is, you do not need to show the registers or feedback loop, only the circuit encoding the logic. Use only gates with an arity of 2. (Hint: this circuit should have 3 inputs and 3 outputs).
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