Example-6.1 For a byte addressable system, the virtual memory address space is 32 bits the physical memory address space is 16 bits. (a) Assume the system uses a two level page table to translate a virtual address to a physical address. Show the format of the virtual address, specify the page size (pick one size if multiple sizes are feasible), and specify the length of each field in the virtual address. Make sure that each translation table fits in a page. (b) Assume you add to your system a 4 way set-associative data cache with 16 cache blocks. Each block in the cache holds 8 bytes of data. In order to address a specific byte of data, you will have to split the address into the cache tag, cache index and byte select. Which parts of the address would you associate with each component, how long will each component be (in bits) and why? (Note: Assume there are no modifiers bits in the table). (c) The main memory access time is 100 ns, and the cache lookup time is 50 ns. Assuming a cache hít rate of 90%, what is the average time to read a location from main memory? (Note: Assume the cache hit rate is the same for the data and the page translation tables).
Example-6.1 For a byte addressable system, the virtual memory address space is 32 bits the physical memory address space is 16 bits. (a) Assume the system uses a two level page table to translate a virtual address to a physical address. Show the format of the virtual address, specify the page size (pick one size if multiple sizes are feasible), and specify the length of each field in the virtual address. Make sure that each translation table fits in a page. (b) Assume you add to your system a 4 way set-associative data cache with 16 cache blocks. Each block in the cache holds 8 bytes of data. In order to address a specific byte of data, you will have to split the address into the cache tag, cache index and byte select. Which parts of the address would you associate with each component, how long will each component be (in bits) and why? (Note: Assume there are no modifiers bits in the table). (c) The main memory access time is 100 ns, and the cache lookup time is 50 ns. Assuming a cache hít rate of 90%, what is the average time to read a location from main memory? (Note: Assume the cache hit rate is the same for the data and the page translation tables).
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Transcribed Image Text:Example-6.17
For a byte addressable system, the virtual memory address space is 32 bits
nd the physical memory address space is 16 bits.
(a) Assume the system uses a two level page table to translate a virtual address to a physical
address. Show the format of the virtual address, specify the page size (pick one size if
multiple sizes are feasible), and specify the length of each field in the virtual address.
Make sure that each translation table fits in a page.
(b) Assume you add to your system a 4 way set-associative data cache with 16 cache blocks.
Each block in the cache holds 8 bytes of data. In order to address a specific byte of data,
you will have to split the address into the cache tag, cache index and byte select. Which
parts of the address would you associate with each component, how long will each
component be (in bits) and why? (Note: Assume there are no modifiers bits in the table).
(c) The main memory access time is 100 ns, and the cache lookup time is 50 ns. Assuming a
cache hit rate of 90%, what is the average time to read a location from main memory?
(Note: Assume the cache hit rate is the same for the data and the page translation tables).
Transcribed Image Text:(d) To speed up the address translation process we introduce a TLB that has an access time
of 20ns. Assuming the TLB hit rate is 95%, what is the average access time for a memory
operation?
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