### Problem 3: Circuit Analysis3. Examine the circuit in Figure 3. Identify which elements are level-sensitive or edge-triggered.#### Explanation of Figure 3:**Figure 3: Problem 3 Circuit**This diagram illustrates a sequential circuit composed of three D flip-flops. Each flip-flop has a data input (D), a clock input (Clk), a true output (Q), and a complementary output (\( \overline{Q} \)). - The clock input is common to all three flip-flops, indicating that they are synchronized with the same clock signal.- The flip-flops are arranged in series, with: - The first flip-flop's (top) Q outputs labeled as \( Q_a \) and \( \overline{Q}_a \). - The second flip-flop's (middle) Q outputs labeled as \( Q_b \) and \( \overline{Q}_b \). - The third flip-flop's (bottom) Q outputs labeled as \( Q_c \) and \( \overline{Q}_c \).To determine if the flip-flops are level-sensitive or edge-triggered, observe the clock input design:- If the flip-flop changes its state on a specific clock edge (rising or falling), it is edge-triggered.- If it changes its state as long as the clock signal is at a certain level (high or low), it is level-sensitive.In this circuit, the specific details needed to determine the type (level-sensitive vs. edge-triggered) are not given, but typically a D flip-flop is edge-triggered.

If the sequential circuit is operated with the clock signal when it is in Logic High, then that type of triggering is known as Positive level triggering. ... If the sequential circuit is operated with the clock signal when it is in Logic Low, then that type of triggering is known as Negative level triggering. The output of a flip flop can be changed by bring a small change in the input signal. This small change can be brought with the help of a clock pulse or commonly known as a trigger pulse. When such a trigger pulse is applied to the input, the output changes and thus the flip flop is said to be triggered. Flip flops are applicable in designing counters or registers which stores data in the form of multi-bit numbers. But such registers need a group of flip flops connected to each other as sequential circuits. And these sequential circuits require trigger pulses. The number of trigger pulses that is applied to the input of the circuit determines the number in a counter. A single pulse makes the bit move one position, when it is applied onto a register that stores multi-bit data. There are two types of triggering as edge and level triggering. There are two levels in a clock pulse or a signal. One is a high voltage (VH), and the other is low voltage (VL). Level sensitive” = output controlled by the level of the clock input. “ Edge triggered” = output changes only at. the point in time when the clock changes from value to the other. There are mainly four types of pulse-triggering methods. High Level Triggering When a flip flop is required to respond at its HIGH state, a HIGH level triggering method is used. It is mainly identified from the straight lead from the clock input. 2. Low Level Triggering When a flip flop is required to respond at its LOW state, a LOW level triggering method is used.. It is mainly identified from the clock input lead along with a low state indicator bubble. 3. Positive Edge Triggering When a flip flop is required to respond at a LOW to HIGH transition state, POSITIVE edge triggering method is used. It is mainly identified from the clock input lead along with a triangle. 4.Negative Edge Triggering When a flip flop is required to respond during the HIGH to LOW transition state, a NEGATIVE edge triggering method is used.. It is mainly identified from the clock input lead along with a low-state indicator and a triangle. Difference between Edge Trigger and Level Trigger: Edge Trigger Level Trigger 1.Type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. 1.Type of triggering that allows a circuit to become active when the clock pulse is on a particular level. 2.An event occurs at the rising edge or falling edge. 2. An event occurs during the high voltage or low voltage level. 3.Flip flop are edge triggered. Latches are level triggered. Triggering: This means making a circuit active. Making a circuit active means allowing the circuit to take input and give output. Like for example supposed we have a flip-flop. When the circuit is not triggered, even if you give some input data, it will not change the data stored inside the flip-flop nor will it change the output Q or Q'. Now there are basically two types of triggering. The triggering is given in form of a clock pulse or gating signal. Depending upon the type of triggering mechanism used, the circuit will become active at specific states of the clock pulse. Level Triggering:In level triggering the circuit will become active when the gating or clock pulse is on a particular level. This level is decided by the designer. We can have a negative level triggering in which the circuit is active when the clock signal is low or a positive level triggering in which the circuit is active when the clock signal is high. Edge Triggering:In edge triggering the circuit becomes active at negative or positive edge of the clock signal. For example if the circuit is positive edge triggered, it will take input at exactly the time in which the clock signal goes from low to high. Similarly input is taken at exactly the time in which the clock signal goes from high to low in negative edge triggering. But keep in mind after the the input, it can be processed in all the time till the next input is taken. Working of D Flip Flop: The D Flip Flopis by far the most important of all the clocked flip-flops. By adding an inverter (NOT gate) between the Set and Reset inputs, the S and R inputs become complements of each other ensuring that the two inputs S and R are never equal (0 or 1) to each other at the same time allowing us to control the toggle action of the flip-flop using one single D (Data) input. Then this Data input, labelled “D” and is used in place of the “Set” signal, and the inverter is used to generate the complementary “Reset” input thereby making a level-sensitive D-type flip-flop from a level-sensitive SR-latch as now S = D and R = not D We remember that a simple SR flip-flop requires two inputs, one to “SET” the output and one to “RESET” the output. By connecting an inverter (NOT gate) to the SR flip-flop we can “SET” and “RESET” the flip-flop using just one input as now the two input signals are complements of each other. This complement avoids the ambiguity inherent in the SRlatch when both inputs are LOW, since that state is no longer possible. Thus this single input is called the “DATA” input. If this data input is held HIGH the flip flop would be “SET” and when it is LOW the flip flop would change and become “RESET”. However, this would be rather pointless since the output of the flip flop would always change on every pulse applied to this data input. To avoid this an additional input called the “CLOCK” or “ENABLE” input is used to isolate the data input from the flip flop’s latching circuitry after the desired data has been stored. The effect is that Dinput condition is only copied to the output Q when the clock input is active. This then forms the basis of another sequential device called a D Flip Flop. The “D flip flop” will store and output whatever logic level is applied to its data terminal so long as the clock input is HIGH. Once the clock input goes LOW the “set” and “reset” inputs of the flip-flop are both held at logic level “1” so it will not change state and store whatever data was present on its output before the clock transition occurred. In other words the output is “latched” at either logic “0” or logic “1”. In this diagram second D flip flop is Positive Edge trigger and Third D flip flop is Negative Edge trigger.