D- D1 Q1 Data Path D2 Q2 FF1 FF2 CLKA CLKB Routing Delay SYSCK For a given sequential circuit as shown below, assume that both the flip flops have a clock to output delay = 10ns, setup time3D5ns and hold time=2ns. Also assume that the combinatorial data path has a delay of 10ns. Calculate the maximum frequency of CLKA that is possible for design to operate correctly

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