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ECE 520 - VLSI Design (spring 2024) 1. Due in class: Thursday April 11, 2024 Homework #8 The following is the layout of an inverter with dimensions. Assume that VDD=2.5V, K'n=100uA/V², Vtn=0.4V, K'p=60uA/V², Vtp=-0.5V, tox=12nm, εox=3.9, Xd=42nm (overlap distance under the gate), C=0.74fF/um², Cjsw=0.43fF/um for both NMOS and PMOS devices at zero bias. a. Estimate the effective input capacitance of the inverter, Cin. b. Estimate the effective output capacitance of the inverter, Cout. For simplicity find effective Cout at zero bias. c. If the output of this inverter is connected to a similar inverter, estimate the tpHL and tpLH. Ignore the wire parasitic capacitance. GND A (input) 0.6um 0.6um Z (output) 0.5um ←>> 0.25um VDD 0.5um 0.25um

ECE 520 - VLSI Design (spring 2024) 1. Due in class: Thursday April 11, 2024 Homework #8 The following is the layout of an inverter with dimensions. Assume that VDD=2.5V, K'n=100uA/V², Vtn=0.4V, K'p=60uA/V², Vtp=-0.5V, tox=12nm, εox=3.9, Xd=42nm (overlap distance under the gate), C=0.74fF/um², Cjsw=0.43fF/um for both NMOS and PMOS devices at zero bias. a. Estimate the effective input capacitance of the inverter, Cin. b. Estimate the effective output capacitance of the inverter, Cout. For simplicity find effective Cout at zero bias. c. If the output of this inverter is connected to a similar inverter, estimate the tpHL and tpLH. Ignore the wire parasitic capacitance. GND A (input) 0.6um 0.6um Z (output) 0.5um ←>> 0.25um VDD 0.5um 0.25um

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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ECE 520 - VLSI Design (spring 2024) 1. Due in class: Thursday April 11, 2024 Homework #8 The following is the layout of an inverter with dimensions. Assume that VDD=2.5V, K'n=100uA/V², Vtn=0.4V, K'p=60uA/V², Vtp=-0.5V, tox=12nm, εox=3.9, Xd=42nm (overlap distance under the gate), C=0.74fF/um², Cjsw=0.43fF/um for both NMOS and PMOS devices at zero bias. a. Estimate the effective input capacitance of the inverter, Cin. b. Estimate the effective output capacitance of the inverter, Cout. For simplicity find effective Cout at zero bias. c. If the output of this inverter is connected to a similar inverter, estimate the tpHL and tpLH. Ignore the wire parasitic capacitance. GND A (input) 0.6um 0.6um Z (output) 0.5um ←>> 0.25um VDD 0.5um 0.25um
Transcribed Image Text:ECE 520 - VLSI Design (spring 2024) 1. Due in class: Thursday April 11, 2024 Homework #8 The following is the layout of an inverter with dimensions. Assume that VDD=2.5V, K'n=100uA/V², Vtn=0.4V, K'p=60uA/V², Vtp=-0.5V, tox=12nm, εox=3.9, Xd=42nm (overlap distance under the gate), C=0.74fF/um², Cjsw=0.43fF/um for both NMOS and PMOS devices at zero bias. a. Estimate the effective input capacitance of the inverter, Cin. b. Estimate the effective output capacitance of the inverter, Cout. For simplicity find effective Cout at zero bias. c. If the output of this inverter is connected to a similar inverter, estimate the tpHL and tpLH. Ignore the wire parasitic capacitance. GND A (input) 0.6um 0.6um Z (output) 0.5um ←>> 0.25um VDD 0.5um 0.25um
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