Each gate presents a load L=1 to the gate drvivng it. Sum and Cout are both driving a load of L=1. Given the gate delays in the table, what is the full adder's worst propagation delay (in ns)

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Each gate presents a load L=1 to the gate drvivng it. Sum and Cout are both driving a load of L=1. Given the gate delays in the table, what is the full adder's worst propagation delay (in ns)?

Gate
AND2
XOR2
OR2
tpLH (ns)
0.16 + 0.038L
0.16 + 0.039L
0.13 + 0.037L
tpHL (ns)
0.17 + 0.018L
0.46 + 0.026L
0.3 + 0.020L
Transcribed Image Text:Gate AND2 XOR2 OR2 tpLH (ns) 0.16 + 0.038L 0.16 + 0.039L 0.13 + 0.037L tpHL (ns) 0.17 + 0.018L 0.46 + 0.026L 0.3 + 0.020L
A
B
Cin-
5
-S
-Cout
Transcribed Image Text:A B Cin- 5 -S -Cout
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