please full answer with clear explanition for each step. Please do the following problems:Draw the circuit and determine(a) Cin(b) Parasitic delay (P)(c) Logical effort (g)for the following gates.14-input NAND2 n-input NAND3 4-input NOR4 n-input NOR5 2-input XORSee Table 4.2 on p. 156 for some final answers. 156Chapter 4Delay4.4.1 Logical EffortLogical effort of a gate is defined as the ratio of the input capacitance of the gate to the inputcapacitance of an inverter that can deliver the same output current. Equivalently, logical effortindicates how much worse a gate is at producing output current as compared to aninverter, given that each input of the gate may only present as much input capacitance asthe inverter.ACin = 3g = 3/3(a)Logical effort can be measured in simulation from delay vs. fanout plots as the ratio ofthe slope of the delay of the gate to the slope of the delay of an inverter, as will be dis-cussed in Section 8.5.3. Alternatively, it can be estimated by sketching gates. Figure 4.22shows inverter, 3-input NAND, and 3-input NOR gates with transistor widths chosen toachieve unit resistance, assuming PMOS transistors have twice the resistance of nMOStransistors. The inverter presents three units of input capacitance. The NAND presentsfive units of capacitance on each input, so the logical effort is 5/3. Similarly, the NOR pre-sents seven units of capacitance, so the logical effort is 7/3. This matches our expectationthat NANDS are better than NORS because NORS have slow pMOS transistors in series.Table 4.2 lists the logical effort of common gates. The effort tends to increase withthe number of inputs. NAND gates are better than NOR gates because the series transis-tors are nMOS rather than pMOS. Exclusive-OR gates are particularly costly and havedifferent logical efforts for different inputs. An interesting case is that multiplexers builtfrom ganged tristates, as shown in Figure 1.29(b), have a logical effort of 2 independent ofthe number of inputs. This might at first seem to imply that very large multiplexers are justas fast as small ones. However, the parasitic delay does increase with multiplexer size;hence, it is generally fastest to construct large multiplexers out of trees of 4-input multi-plexers [Sutherland99].ACCin = 5g = 5/3(b)YCin = 7g = 7/3(c)FIGURE 4.22 Logic gatessized for unit resistanceTABLE 4.2 Logical effort of common gatesGate TypeNumber of Inputs4ninverter1NAND4/35/36/3(n + 2)/3NOR5/37/39/3(2n + 1)/3tristate, multiplexer2XOR, XNOR4, 46, 12, 68, 16, 16, 84.4.2 Parasitic DelayThe parasitic delay of a gate is the delay of the gate when it drives zero load. It can be esti-mated with RC delay models. A crude method good for hand calculations is to count onlydiffusion capacitance on the output node. For example, consider the gates in Figure 4.22,assuming each transistor on the output node has its own drain diffusion contact. Transis-tor widths were chosen to give a resistance of R in each gate. The inverter has three unitsof diffusion capacitance on the output, so the parasitic delay is 3RC = t. In other words,SThis assumption is made throughout the book. Exercises 4.19-4.20 explore the effects of different relativeresistances (see also [Sutherland99]). The overall conclusions do not change very much, so the simplemodel is good enough for most hand estimates. A simulator or static timing analyzer should be used whenmore accurate results are required.ABC

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Draw the circuit and det (а) Cin (b) Parasitic delay ( (c) Logical effort (g for the following gates. 14-input NAND 2 n-input NAND 3 4-input NOR 4 n-input NOR

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Question

please full answer with clear explanition for each step.

Please do the following problems:
Draw the circuit and determine
(a) Cin
(b) Parasitic delay (P)
(c) Logical effort (g)
for the following gates.
14-input NAND
2 n-input NAND
3 4-input NOR
4 n-input NOR
5 2-input XOR
See Table 4.2 on p. 156 for some final answers.

156
Chapter 4
Delay
4.4.1 Logical Effort
Logical effort of a gate is defined as the ratio of the input capacitance of the gate to the input
capacitance of an inverter that can deliver the same output current. Equivalently, logical effort
indicates how much worse a gate is at producing output current as compared to an
inverter, given that each input of the gate may only present as much input capacitance as
the inverter.
A
Cin = 3
g = 3/3
(a)
Logical effort can be measured in simulation from delay vs. fanout plots as the ratio of
the slope of the delay of the gate to the slope of the delay of an inverter, as will be dis-
cussed in Section 8.5.3. Alternatively, it can be estimated by sketching gates. Figure 4.22
shows inverter, 3-input NAND, and 3-input NOR gates with transistor widths chosen to
achieve unit resistance, assuming PMOS transistors have twice the resistance of nMOS
transistors. The inverter presents three units of input capacitance. The NAND presents
five units of capacitance on each input, so the logical effort is 5/3. Similarly, the NOR pre-
sents seven units of capacitance, so the logical effort is 7/3. This matches our expectation
that NANDS are better than NORS because NORS have slow pMOS transistors in series.
Table 4.2 lists the logical effort of common gates. The effort tends to increase with
the number of inputs. NAND gates are better than NOR gates because the series transis-
tors are nMOS rather than pMOS. Exclusive-OR gates are particularly costly and have
different logical efforts for different inputs. An interesting case is that multiplexers built
from ganged tristates, as shown in Figure 1.29(b), have a logical effort of 2 independent of
the number of inputs. This might at first seem to imply that very large multiplexers are just
as fast as small ones. However, the parasitic delay does increase with multiplexer size;
hence, it is generally fastest to construct large multiplexers out of trees of 4-input multi-
plexers [Sutherland99].
A
C
Cin = 5
g = 5/3
(b)
Y
Cin = 7
g = 7/3
(c)
FIGURE 4.22 Logic gates
sized for unit resistance
TABLE 4.2 Logical effort of common gates
Gate Type
Number of Inputs
4
n
inverter
1
NAND
4/3
5/3
6/3
(n + 2)/3
NOR
5/3
7/3
9/3
(2n + 1)/3
tristate, multiplexer
2
XOR, XNOR
4, 4
6, 12, 6
8, 16, 16, 8
4.4.2 Parasitic Delay
The parasitic delay of a gate is the delay of the gate when it drives zero load. It can be esti-
mated with RC delay models. A crude method good for hand calculations is to count only
diffusion capacitance on the output node. For example, consider the gates in Figure 4.22,
assuming each transistor on the output node has its own drain diffusion contact. Transis-
tor widths were chosen to give a resistance of R in each gate. The inverter has three units
of diffusion capacitance on the output, so the parasitic delay is 3RC = t. In other words,
SThis assumption is made throughout the book. Exercises 4.19-4.20 explore the effects of different relative
resistances (see also [Sutherland99]). The overall conclusions do not change very much, so the simple
model is good enough for most hand estimates. A simulator or static timing analyzer should be used when
more accurate results are required.
ABC

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