Draw a state diagram to design an ordered logic circuit with an output of 1 if 1011 is entered in sequence.
Draw a state diagram to design an ordered logic circuit with an output of 1 if 1011 is entered in sequence.
Computer Networking: A Top-Down Approach (7th Edition)
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Publisher:James Kurose, Keith Ross
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Draw a state diagram to design an ordered logic circuit with an output of 1 if 1011 is entered in sequence.
Transcribed Image Text:Given sequence to be detected is 1011
Consider sequence detector diagram as below
X
Input
sequence
Clock
Mealy state graph for this sequence detector is
S₁-01
S₂=10
S,=11
AB
00
01
10
11
AB
S₁
Present
State with
input
00
0/0
01
AB
State table for the given sequence detector
Present Next State Present
state X=0 X=1 X = 0
So
S₂
0
S₁
S₂
0
S₂ S₂
S₂
0
S₂ So S₁ 0
00
K-map for T
0 1
X
10
10
T₁ = AB+BX
K-map for T₂
AB
Here four states are there so we need two flip flops
Consider states as below
S,=00
ABX
000
001
010
011
100
101
110
111
00
Consider three flip flops A and B
State table for the above sequence detector
01 T
İ
11 0
01
11 1 1
11
So
So
10
Sequence
Detector
0/0
X
So
X
0 1
0/0
0
T₂ = ABX
0/0
1/1
T₂ = AX +BX+ AX
K-map for Z
1
AB AB Present output
X=0 X=1
X=0
X = 1
00
01
0
0
00
10
0
0
11
10
0
0
00
01
0
1
Next
State
A*B*
→ Z
Sequence
detection
signal
00
01
1/0
S₂
00
10
10
11
00
01
Required sequence detector
S₁
output
X = 1
0
0
1/0
1/0
0
0
1
0
0
1
0
0
1
1
Exitation Table
T₁
TB
0
1
1
1
1
0
1
0
Output
Z
0
0
0
0
0
0
0
1
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