) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.) (Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.)

) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.) (Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.)

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question

Q1
a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter
should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate
the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated
waveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.)
(Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and
OFFTIME accordingly for the clock source.)
Part
DigClock
Part List:
OFFTIME = .5uS DSTM1
ONTIME = .5us
DELAY =
STARTVAL = 0
OPPVAL = 1
DisClock
FileStm1
FieStm16
CLK
FileStim2
FileStim32
FileStim4
FileStime
Libraries
Design Cache
EVAL
1.
SOURCE

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