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Design a sequential circuit with two T flip-flops A and B and two inputs E and Fand a reset which will satisfy the following design requirements. If E=0, the circuit remains in the same state regardless of the value of F. When E=1 and F=1, the circuit goes through the state transitions from 00 to 01, to 10, to 11, back to 00, and repeats. When E=1 and F=0, the circuit goes through the state transitions from 00 to 11, to 10, to 01, back to 00, and repeats. The results should be consistent with the simulation timing diagrams shown below. 1. Draw a state diagram for this requirement using the template below. 2. Draw a present state / next state table for this requirement using the template below. 3. Use Karnaugh maps to determine the flip flop minimized Boolean input expressions. 4. Model the design requirement using Verilog structural source code. Use T flip- flops. Provide the source code. 5. Simulate the structural model using a test bench with stimulus test signals as shown in the simulation timing diagrams below. Provide waveform simulation results. 6. Provide a logic diagram for this structural design from the RTL Analysis tool in Vivado.

Design a sequential circuit with two T flip-flops A and B and two inputs E and Fand a reset which will satisfy the following design requirements. If E=0, the circuit remains in the same state regardless of the value of F. When E=1 and F=1, the circuit goes through the state transitions from 00 to 01, to 10, to 11, back to 00, and repeats. When E=1 and F=0, the circuit goes through the state transitions from 00 to 11, to 10, to 01, back to 00, and repeats. The results should be consistent with the simulation timing diagrams shown below. 1. Draw a state diagram for this requirement using the template below. 2. Draw a present state / next state table for this requirement using the template below. 3. Use Karnaugh maps to determine the flip flop minimized Boolean input expressions. 4. Model the design requirement using Verilog structural source code. Use T flip- flops. Provide the source code. 5. Simulate the structural model using a test bench with stimulus test signals as shown in the simulation timing diagrams below. Provide waveform simulation results. 6. Provide a logic diagram for this structural design from the RTL Analysis tool in Vivado.

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Design a sequential circuit with two T flip-flops A and B and two inputs E and F and a reset which will satisfy the following design requirements. If E=0, the circuit remains in the same state regardless of the value of F. When E=1 and F=1, the circuit goes through the state transitions from 00 to 01, to 10, to 11, back to 00, and repeats. When E=1 and F=0, the circuit goes through the state transitions from 00 to 11, to 10, to 01, back to 00, and repeats. The results should be consistent with the simulation timing diagrams shown below. 1. Draw a state diagram for this requirement using the template below. 2. Draw a present state / next state table for this requirement using the template below. 3. Use Karnaugh maps to determine the flip flop minimized Boolean input expressions. 4. Model the design requirement using Verilog structural source code. Use T flip- flops. Provide the source code. 5. Simulate the structural model using a test bench with stimulus test signals as shown in the simulation timing diagrams below. Provide waveform simulation results. 6. Provide a logic diagram for this structural design from the RTL Analysis tool in Vivado. 7. Model the circuit using Verilog behavioral source code. Provide the source code. 8. Simulate the behavioral model using a test bench with stimulus test signals as shown in the simulation timing diagrams below. Provide waveform simulation results.
Transcribed Image Text:Design a sequential circuit with two T flip-flops A and B and two inputs E and F and a reset which will satisfy the following design requirements. If E=0, the circuit remains in the same state regardless of the value of F. When E=1 and F=1, the circuit goes through the state transitions from 00 to 01, to 10, to 11, back to 00, and repeats. When E=1 and F=0, the circuit goes through the state transitions from 00 to 11, to 10, to 01, back to 00, and repeats. The results should be consistent with the simulation timing diagrams shown below. 1. Draw a state diagram for this requirement using the template below. 2. Draw a present state / next state table for this requirement using the template below. 3. Use Karnaugh maps to determine the flip flop minimized Boolean input expressions. 4. Model the design requirement using Verilog structural source code. Use T flip- flops. Provide the source code. 5. Simulate the structural model using a test bench with stimulus test signals as shown in the simulation timing diagrams below. Provide waveform simulation results. 6. Provide a logic diagram for this structural design from the RTL Analysis tool in Vivado. 7. Model the circuit using Verilog behavioral source code. Provide the source code. 8. Simulate the behavioral model using a test bench with stimulus test signals as shown in the simulation timing diagrams below. Provide waveform simulation results.
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