Design a combinational circuit with three inputs x, y, and z and three outputs F1, F2, and F3 with the minimum possible number of gates, based on the following specifications: ⚫ The output F1 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a decimal number that is less than decimal 4, otherwise the output is 0. ⚫ The output F2 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a decimal number that is either 4 or an odd decimal number, otherwise the output is 0. ⚫ The output F3 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a decimal number that is either 0 or greater than decimal 4, otherwise the output is 0. a) Your design steps must include: A truth table, K-maps, simplified Boolean expressions in canonical and standard SOP forms, and implementations with logic gates. Combine the logic diagrams into a single logic circuit having 3 inputs and 3 outputs. In your implementations, assume the inputs and their complements are available b) Identify the minimum number of gates in your design. How many gate-delays from the inputs to each of the three outputs? If the delays from the inputs to each output are not equal, redraw the logic diagram of your circuit with equal delays from the inputs to each output.
Design a combinational circuit with three inputs x, y, and z and three outputs F1, F2, and F3 with the minimum possible number of gates, based on the following specifications: ⚫ The output F1 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a decimal number that is less than decimal 4, otherwise the output is 0. ⚫ The output F2 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a decimal number that is either 4 or an odd decimal number, otherwise the output is 0. ⚫ The output F3 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a decimal number that is either 0 or greater than decimal 4, otherwise the output is 0. a) Your design steps must include: A truth table, K-maps, simplified Boolean expressions in canonical and standard SOP forms, and implementations with logic gates. Combine the logic diagrams into a single logic circuit having 3 inputs and 3 outputs. In your implementations, assume the inputs and their complements are available b) Identify the minimum number of gates in your design. How many gate-delays from the inputs to each of the three outputs? If the delays from the inputs to each output are not equal, redraw the logic diagram of your circuit with equal delays from the inputs to each output.
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Transcribed Image Text:Design a combinational circuit with three inputs x, y, and z and three outputs F1, F2, and F3
with the minimum possible number of gates, based on the following specifications:
⚫ The output F1 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a
decimal number that is less than decimal 4, otherwise the output is 0.
⚫ The output F2 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a
decimal number that is either 4 or an odd decimal number, otherwise the output is 0.
⚫ The output F3 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a
decimal number that is either 0 or greater than decimal 4, otherwise the output is 0.
a) Your design steps must include: A truth table, K-maps, simplified Boolean expressions in
canonical and standard SOP forms, and implementations with logic gates.
Combine the logic diagrams into a single logic circuit having 3 inputs and 3 outputs.
In your implementations, assume the inputs and their complements are available
b) Identify the minimum number of gates in your design. How many gate-delays from the
inputs to each of the three outputs? If the delays from the inputs to each output are not
equal, redraw the logic diagram of your circuit with equal delays from the inputs to each
output.
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