Design a circuit that outputs 2's complement of a 3-bit number using encoder &decoder.IC: 74ls138 [decoder]; 74ls148 [encoder]The Truth Table for 2's complement output:InputsOutputsActive LowOutputMintermCВA MintermD2DiDoD2 | D1DO1111171111111114141111131116.1121117111111Report:The report should cover the followings1.Name of the experimentObjectiveRequired Components and EquipmentsExperimental Setup (i.e., diagram of the circuit)Results and Discussions2.3.4.5.a.Draw a circuit diagram with encoder and decoder that will output the 1'scomplement of 3 bit number.b.Can you implement a code converter with encoder and decoder? If yes, how?If no, explain why not?11AOO(A)3*88 to 33decode44 encode A11(B)A22(C)6.77 74138DATA QUTPUTSYOY!Y2Y3Y4 Y515141312 1YOYIV2V3Y4Y5Y6G2AG28G1Y7G2AG2BG1Y7GNDOUTPUTSEL ECTENABLE74148OUTPUTSINPUTSOUTPUTVcCEOGS32A0161514131211109EOGS21AO7ElA2A11.346.7847E1A2A1GNDINPUTSOUTPUTS

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Design a circuit that outputs 2's complement of a 3-bit number using encoder & decoder. IC: 74ls138 [decoder]; 74ls148 [encoder] The Truth Table for 2's complement output:

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

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Question

Design a circuit that outputs 2's complement of a 3-bit number using encoder &
decoder.
IC: 74ls138 [decoder]; 74ls148 [encoder]
The Truth Table for 2's complement output:
Inputs
Outputs
Active Low
Output
Minterm
C
В
A Minterm
D2
Di
Do
D2 | D1
DO
1
1
1
1
1
7
1
1
1
1
1
1
1
1
1
4
1
4
1
1
1
1
1
3
1
1
1
6.
1
1
2
1
1
1
7
1
1
1
1
1
1
Report:
The report should cover the followings
1.
Name of the experiment
Objective
Required Components and Equipments
Experimental Setup (i.e., diagram of the circuit)
Results and Discussions
2.
3.
4.
5.
a.
Draw a circuit diagram with encoder and decoder that will output the 1's
complement of 3 bit number.
b.
Can you implement a code converter with encoder and decoder? If yes, how?
If no, explain why not?
1
1
AO
O(A)
3*8
8 to 3
3
decode
4
4 encode A1
1(B)
A2
2(C)
6.
7
7

74138
DATA QUTPUTS
YO
Y!
Y2
Y3
Y4 Y5
15
14
13
12 1
YO
YI
V2
V3
Y4
Y5
Y6
G2A
G28
G1
Y7
G2A
G2B
G1
Y7
GND
OUTPUT
SEL ECT
ENABLE
74148
OUTPUTS
INPUTS
OUTPUT
VcC
EO
GS
3
2
A0
16
15
14
13
12
11
10
9
EO
GS
2
1
AO
7
El
A2
A1
1.
3
4
6.
7
8
4
7
E1
A2
A1
GND
INPUTS
OUTPUTS

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