Solve part D using the chart from part C c. Now assume that the program can be executed in 4 parallel tasks or threads with roughlyequal number of instructions executed in each task. In another words, as the program isparallelized to run over multiple cores, the number of instructions per processor is dividedby the number of cores. Execution is on a quadcore system with each core (processor)having the same performance as the single processor originally used for Machine B.Coordination and synchronization between the parts adds an extra 50,000 instructionexecutions to each task. Assume the same instruction mix as for Machine B for each task,but increase the CPI for memory reference with cache miss to 10 cycles due to contentionfor memory.Fill out the table below for Machine C.MachineBInstruction TypeLogic and ArithmeticBranchLoad Store with cache hitMemory reference with cache miSSLogic and ArithmeticLoad/Store with cache hitMemory reference with cache miss118Instruction Mix (9)1060 d. Determine the average CPI, MIPS rate, and execution time for Machine C.

Answered: d. Determine the average CPI, MIPS…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Related questions

Concept explainers

Question

Solve part D using the chart from part C

c. Now assume that the program can be executed in 4 parallel tasks or threads with roughly
equal number of instructions executed in each task. In another words, as the program is
parallelized to run over multiple cores, the number of instructions per processor is divided
by the number of cores. Execution is on a quadcore system with each core (processor)
having the same performance as the single processor originally used for Machine B.
Coordination and synchronization between the parts adds an extra 50,000 instruction
executions to each task. Assume the same instruction mix as for Machine B for each task,
but increase the CPI for memory reference with cache miss to 10 cycles due to contention
for memory.
Fill out the table below for Machine C.
Machine
B
Instruction Type
Logic and Arithmetic
Branch
Load Store with cache hit
Memory reference with cache miSS
Logic and Arithmetic
Load/Store with cache hit
Memory reference with cache miss
1
1
8
Instruction Mix (9)
10
60

d. Determine the average CPI, MIPS rate, and execution time for Machine C.

Expert Solution

Step 1: Given

Machine | Instruction Type | CPI | Instruction Mix (%)
| Logic and Arithmetic | 1 | 10
| Branch | 2 | 12
B | Load/Store with cache hit | 4 | 18
| Memory reference with cache miss | 8 | 60
-------------------------------------------------------------------------------
| Logic and Arithmetic | 1 | 10
| Branch | 2 | 12
C | Load/Store with cache hit | 4 | 18
| Memory reference with cache miss | 10 | 60
-------------------------------------------------------------------------------

For Machine C, we maintain the same instruction types as Machine B, which are Logic and Arithmetic, Branch, Load/Store with cache hit, and Memory reference with cache miss.

We update the CPI values for Machine C according to the given information. Specifically, we increase the CPI for Memory reference with cache miss to 10 cycles due to contention for memory.

The instruction mix percentages remain the same as Machine B: 10% for Logic and Arithmetic, 12% for Branch, 18% for Load/Store with cache hit, and 60% for Memory reference with cache miss.

Step by step

Solved in 3 steps

SEE SOLUTION Check out a sample Q&A here

Knowledge Booster

Learn more about

Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.

Similar questions