CSC 215 Exam 2 Name Fatema 1. Design a combinational circuit that converts a four-bit Gray code A, B, C, D (a binary numeral system where two successive values differ in only one bit, shown as table blow) to a bit four-binary number w, x, y, z. ABCD wxyz 0000 0000 0001 0001 0011 0010 4 0010 0011 0110 0100 4 0111 0101 g 0101 0110 6 0100 0111 1100 1000 1101 1001 1111 1010 1110 1011 1010 1100 1011 1101 b) Do the circuit (5 1001 1110 1000 1111 1x2 a) Using Karnaugh maps, obtain a minimum sum-of-products form w, x, y, and z. (20 points) 0:1 1.0 10 00 h map for W 92 92 90 2 9-21 10 O 0 0 D 0 ωχ 6.1. ド 0 1 1 1

The circuit shown in Figure 02 is a 4-bit circuit that can add or subtract numbers in a form used in computers (positive numbers in true form; negative numbers in complement form). (a) Explain what happens when the Add Subt. input is HIGH. (b) What happens when Add/Subt. is LOW? Q.5 A, B2 A B1 A, Bo Az B3 Add/Subt. O A B Cin A B Cin A B Cin A B Cin Cout Cout Σ Σ Cout Σ Cout Σ FIGYRE 02

A Gray code is a sequence of binary numbers with the property that no more than 1 bit changes in going from one element of the sequence to another. For example, here is a 3-bit binary Gray code: 000, 001, 011, 010, 110, 111, 101, and 100. Using three D flip-flops and a PLA, construct a 3-bit Gray code counter that has two inputs: reset, which sets the counter to 000, and inc, which makes the counter go to the next value in the sequence. Note that the code is cyclic, so that the value after 100 in the sequence is 000.

The given function table is for an eight-bit ALU circuit with Bounded Signed Integers in Two’s Complement Representation. Modify it to represent signed 4-bit two's complement representation.

Part 1 - Adders Let's consider a 8 bits precision system: a. Represent the number 81 in this system b. Represent the numbers 42 in this system c. Perform the following operation S = 81 +42 d. Represent the number (-42) within this binary system using the 2's complement representation e. Perform the following subtraction R = 42 - 81 in this system and prove that R = - 39 Let's consider that we have an IC that implements a four (4) bits adder. Use this IC to design an 8 bits adder g. Realize the addition S= 81 + 42 in this adder. You should write near each input and output operands of the ICs the value of each bit representing the Sum S f. h. Using the same design of question f, and any other additional circuitry, design a circuit that can realize a subtraction i. Simulate the subtraction presented in e. by showing the value of each input and output operands of the IC j. Simulate the addition presented in c. in this adder/subtractor by showing the value of each input and output operands…

Computer architecture hw help 2

write out work and show work

A circuit has four inputs p,q,r,s representing the natural binary number 0000=0,to 1111=15 p is the most significant bit .the circuit has one output, x,which is true if the input to the circuit represent is a prime number and false other wise  (A) design a true table for this circuit, and hence obtain an expression for x in terms of P,Q,R,S.

Generate a RAC parity matrix for a (20, 12) coding of the data word 111001010001. Use the grid shown below (or a similar one). Explain your work. What are the limitations of this technique?

Add the following BCD numbers:(a) 0010 + 0001 (b) 0101 + 0011(c) 0111 + 0010 (d) 1000 + 0001(e) 00011000 + 00010001 (f) 01100100 + 00110011(g) 01000000 + 01000111 (h) 10000101 + 00010011