Create VHDL files using dataflow, structural and behavioral modeling of any logic gates (choose one - or, nand, nor, xor, xnor) except AND gate. 3 projects - 1 main circuit and 1 testbench for each project You may use and_gate_tb testbench. Take a screenshot (full Monitor) of the code and output for each modeling (1page per modelling). 3 Modelling must be placed in a single pdf file Ex. GATE: AND GATE DESIGN AND TEST BENCH: Behavioral Modeling

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