Create VHDL files using dataflow, structural and behavioral modeling of any logic gates (choose one - or, nand, nor, xor, xnor) except AND gate. 3 projects – 1 main circuit and 1 testbench for each project You may use and_gate_tb testbench.

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ASSIGNMENT 2.1 VHDL
Create VHDL files using dataflow, structural and behavioral modeling of any logic
gates (choose one - or, nand, nor, xor, xnor) except AND gate.
3 projects – 1 main circuit and 1 testbench for each project
You may use and_gate_tb testbench.
Transcribed Image Text:ASSIGNMENT 2.1 VHDL Create VHDL files using dataflow, structural and behavioral modeling of any logic gates (choose one - or, nand, nor, xor, xnor) except AND gate. 3 projects – 1 main circuit and 1 testbench for each project You may use and_gate_tb testbench.
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