Create a verilog program for the following condition: if w3=0, display down counter if w3=1, display up counter Please refer to the output of the program together with the source code Note: Please use the Source Code that I provided to be able to determine the same result.
Create a verilog program for the following condition: if w3=0, display down counter if w3=1, display up counter Please refer to the output of the program together with the source code Note: Please use the Source Code that I provided to be able to determine the same result.
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
Related questions
Question
Course: Introduction to Hardware Language (HDL)
Topic: while Statement verilog (BCD While if)
Create a verilog program for the following condition:
- if w3=0, display down counter
- if w3=1, display up counter
- Please refer to the output of the program together with the source code
- Note: Please use the Source Code that I provided to be able to determine the same result.
Transcribed Image Text:C:\iverilog\bin>vvp digit_while3
time
w3w2w1w0 Y
0000
0111
1
0001
0110
2
3
0010
0101
0011
0100
4
5
0100
0011
0101
0010
0110
0001
7
8
9
10
11
12
13
0111
0000
1000
0001
1001
0010
1010
0011
1011
0100
1100
0101
1101
0110
14
1110
0111
15
1111
1000
![module whilel (y,w3,w2,wl,w0);
input [3:0]w3,w2,w1,w0;
output [3:0]y;
4
5
7
reg [3:0]y;
reg [3:0]k;
8.
10
11
always e (w)
Ebegin
13
if
(w[2]==1'b0)
14
y=4'b0000;
15
else
begin
y=0;|
16
17
18
k=0;
19
while (k<w)
20
begin
у %3D у +1;
k + 1;
21
22
k
23
end
24
end
25
end
26
endmodule
27
28
module TestBench;
29
reg [2:0]w;
wire [3:0]y;
30
31
initial begin
$display ("Time
w = 1'b0;
#15 $finish;
32
Y");
W
33
34
35
end
36
always #1 w=w+1;
37
38
whilel Ul (y, w);
39
initial
40
Smonitor ("%g
%b
%b",$time,w,y);
41
endmodule
H 1 1 11- H H H NN N N N N NN N ONM M M m m m m m m m 4](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F482fe49c-654b-443c-a977-33a9539e4319%2F248fc961-3a51-4686-bec6-383f63826fe5%2F6hebs4r_processed.png&w=3840&q=75)
Transcribed Image Text:module whilel (y,w3,w2,wl,w0);
input [3:0]w3,w2,w1,w0;
output [3:0]y;
4
5
7
reg [3:0]y;
reg [3:0]k;
8.
10
11
always e (w)
Ebegin
13
if
(w[2]==1'b0)
14
y=4'b0000;
15
else
begin
y=0;|
16
17
18
k=0;
19
while (k<w)
20
begin
у %3D у +1;
k + 1;
21
22
k
23
end
24
end
25
end
26
endmodule
27
28
module TestBench;
29
reg [2:0]w;
wire [3:0]y;
30
31
initial begin
$display ("Time
w = 1'b0;
#15 $finish;
32
Y");
W
33
34
35
end
36
always #1 w=w+1;
37
38
whilel Ul (y, w);
39
initial
40
Smonitor ("%g
%b
%b",$time,w,y);
41
endmodule
H 1 1 11- H H H NN N N N N NN N ONM M M m m m m m m m 4
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