Convert the code from Verilog to Vhdlmodule wav_player (input CLK,input switch_play,output reg audio_out);1234localparam MEM_SIZE = 36130; //reg [7:0] memory[MEM_SIZE-1:0];initial begin$readmemh ("01_05_b36130.txt", memory);810endwire s_start;debouncer dl(.CLK (CLK),..switch_input (switch_play),.trans_up (s_start));111213reg play = 0;reg [5:0] prescaler;141516reg [7:0] counter;17reg [19:0] address;18reg [7:0] value;19always e (posedge CLK)beginif (play)202122beginprescaler <= prescaler + 1;if (prescaler == 24)232425// 8kHz x 256 steps = 2.048 MHz26begin27prescaler <= 0;28counter <= counter + 1;29value <= memory[address];audio_out <= (value > counter);if (counter == 255)begin30313233address <= address + 1;if (address ==beginplay <= 0;34MEM_SIZE)353637address <=38end39end40end41end42if (s_start)43begin44play <= 1;45end46end47

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Convert the code from Verilog to Vhdl 1 module wav_player ( input CLK, input switch_play, output reg audio_out ); 4 localparam MEM_SIZE = 36130; // reg [7:0] memory[MEM_SIZE-1:0]; initial begin $readmemh ("01_05_b36130.txt", memory); %3D 8 10 end 11 wire s_start; 12 debouncer dl (.CLK (CLK),.switch_input (switch_play), .trans_up (s_start)); 13 14 reg play = 0; 15 reg [5:0] prescaler; 16 reg [7:0] counter; 17 reg [19:0] address; reg [7:0] value; 18 19 20 always @ (posedge CLK) 123 567

Convert the code from Verilog to Vhdl 1 module wav_player ( input CLK, input switch_play, output reg audio_out ); 4 localparam MEM_SIZE = 36130; // reg [7:0] memory[MEM_SIZE-1:0]; initial begin $readmemh ("01_05_b36130.txt", memory); %3D 8 10 end 11 wire s_start; 12 debouncer dl (.CLK (CLK),.switch_input (switch_play), .trans_up (s_start)); 13 14 reg play = 0; 15 reg [5:0] prescaler; 16 reg [7:0] counter; 17 reg [19:0] address; reg [7:0] value; 18 19 20 always @ (posedge CLK) 123 567

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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