Convert the code from Verilog to Vhdl 1 module wav_player ( input CLK, input switch_play, output reg audio_out ); 4 localparam MEM_SIZE = 36130; // reg [7:0] memory[MEM_SIZE-1:0]; initial begin $readmemh ("01_05_b36130.txt", memory); %3D 8 10 end 11 wire s_start; 12 debouncer dl (.CLK (CLK),.switch_input (switch_play), .trans_up (s_start)); 13 14 reg play = 0; 15 reg [5:0] prescaler; 16 reg [7:0] counter; 17 reg [19:0] address; reg [7:0] value; 18 19 20 always @ (posedge CLK) 123 567

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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Convert the code from Verilog to Vhdl
module wav_player (
input CLK,
input switch_play,
output reg audio_out
);
1
2
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4
localparam MEM_SIZE = 36130; //
reg [7:0] memory[MEM_SIZE-1:0];
initial begin
$readmemh ("01_05_b36130.txt", memory);
8
10
end
wire s_start;
debouncer dl(.CLK (CLK),..switch_input (switch_play),.trans_up (s_start));
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reg play = 0;
reg [5:0] prescaler;
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reg [7:0] counter;
17
reg [19:0] address;
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reg [7:0] value;
19
always e (posedge CLK)
begin
if (play)
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begin
prescaler <= prescaler + 1;
if (prescaler == 24)
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25
// 8kHz x 256 steps = 2.048 MHz
26
begin
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prescaler <= 0;
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counter <= counter + 1;
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value <= memory[address];
audio_out <= (value > counter);
if (counter == 255)
begin
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address <= address + 1;
if (address ==
begin
play <= 0;
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MEM_SIZE)
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address <=
38
end
39
end
40
end
41
end
42
if (s_start)
43
begin
44
play <= 1;
45
end
46
end
47
Transcribed Image Text:Convert the code from Verilog to Vhdl module wav_player ( input CLK, input switch_play, output reg audio_out ); 1 2 3 4 localparam MEM_SIZE = 36130; // reg [7:0] memory[MEM_SIZE-1:0]; initial begin $readmemh ("01_05_b36130.txt", memory); 8 10 end wire s_start; debouncer dl(.CLK (CLK),..switch_input (switch_play),.trans_up (s_start)); 11 12 13 reg play = 0; reg [5:0] prescaler; 14 15 16 reg [7:0] counter; 17 reg [19:0] address; 18 reg [7:0] value; 19 always e (posedge CLK) begin if (play) 20 21 22 begin prescaler <= prescaler + 1; if (prescaler == 24) 23 24 25 // 8kHz x 256 steps = 2.048 MHz 26 begin 27 prescaler <= 0; 28 counter <= counter + 1; 29 value <= memory[address]; audio_out <= (value > counter); if (counter == 255) begin 30 31 32 33 address <= address + 1; if (address == begin play <= 0; 34 MEM_SIZE) 35 36 37 address <= 38 end 39 end 40 end 41 end 42 if (s_start) 43 begin 44 play <= 1; 45 end 46 end 47
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