Computer science machine organization question ### Instruction Analysis and Data Path Diagram Explanation#### Questions and Answers:Consider these instructions: ST, LDR, ADD, JSR, BR.a) **Which instructions use ADDR2MUX?** - ST (Store) - LDR (Load Register) - JSR (Jump to Subroutine)b) **Which instructions use the register file?** - ST (for storing register contents to memory) - LDR (for loading contents to register from memory) - ADD (for arithmetic operations) - JSR (for saving the return address) - BR (for branching based on register contents)c) **Which instructions use the ALU?** - ST (for address calculation) - LDR (for address calculation) - ADD (for arithmetic operations) - JSR (for address calculation) - BR (for address calculation)d) **Which instructions use the MEMORY?** - ST (Store) - LDR (Load Register) - JSR (Jump to Subroutine, for memory access to save the return address)#### Data Path Diagram Explanation:![Data Path Diagram]This data path diagram illustrates the various components and connections within a computer architecture. Below is a detailed explanation of the major components and their interactions:1. **Program Counter (PC) and PCMUX**: - The PC holds the address of the current instruction. PCMUX selects the next address for the PC through an increment or other input sources.2. **Instruction Register (IR)**: - The IR holds the current instruction being executed.3. **Register File**: - This includes registers SR1 and SR2 for source operands and DR for the destination register. Data from these registers can be output through SR1 OUT and SR2 OUT paths.4. **Address MUXes (ADDR1MUX, ADDR2MUX)**: - ADDR1MUX and ADDR2MUX select the address sources for address calculations. ADDR2MUX handles different immediate values and register-based addressing.5. **Sign Extension Units (SEXT)**: - These units extend immediate values to the required bit width for address calculations.6. **ALU**: - The Arithmetic Logic Unit performs arithmetic and logical operations. It receives inputs through the ALUK selection signals.7. **Finite State Machine**: - This controls the sequence of operations and states during instruction execution.

This question is related to Computer architecture. I'll discuss one by one next step onwards.

Consider these instructions: ST, LDR, ADD, JSR, BR. a) Which instructions use ADDR2MUX? b) Which instructions use the register file? c) Which instructions use the ALU? d) Which instructions use the MEMORY? GateMARMUX GatePC MARMUX LD.IC PC REG DR PCMUX FILE LD.REG- SR2 SRI SR2- OUT ZEXT ADDRIMUX ADDRIMUX ADDR2MUX (100] SEXT SEXT |[4:0] 1801 SEXT ASR2MUX/ (15.9) FINITE 15:01 SEXT R STATE MACHINE ALU ALUK NZP-LD.CC LD.IR- LOGIC -GateALU GateMDRA 16 16 16 LD.MDR- MDR 16 MEMORY MAR -LD.MAR INPUT OUTPUT 16 MEM.ĖN, R.W