Consider the sequential circuit in Figure 5.31 where the adder is a CLA. Its simplified circuit is shown in Figure 5.32. Assuming that the Flip-Flips register set-up time, clock-to-q, and clock-skew are each 0.1 ns, determine the upper bound for its clock frequency. T=0.65 nsclk1Tcs= 0.3 nsclk2Tcg = 0.05 nsd1 Current d1q1 Current a New q1 = d1 currentclk1 causes the changes in d1 to change q1d2Current d2New d2Ad2 =0.25 nsq2Current q2Setup time violationFIGURE 5.38 A timing diagram illustrating a setup or hold-time violation due toclock skew.

For the first flip flop from right in fig. 5.32,the clock-skew time will be, (0.1+0.1)=0.2 ns

Answered: Consider the sequential circuit in…

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

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Consider the sequential circuit in Figure 5.31 where the adder is a CLA. Its simplified circuit is shown in Figure 5.32. Assuming that the Flip-Flips register set-up time, clock-to-q, and clock-skew are each 0.1 ns, determine the upper bound for its clock frequency.

T=0.65 ns
clk1
Tcs= 0.3 ns
clk2
Tcg = 0.05 ns
d1 Current d1
q1 Current a New q1 = d1 current
clk1 causes the changes in d1 to change q1
d2
Current d2
New d2
Ad2 =0.25 ns
q2
Current q2
Setup time violation
FIGURE 5.38 A timing diagram illustrating a setup or hold-time violation due to
clock skew.

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