Consider the circuit shown below. Notice that it utilizes dataflow Verilog operators that you are not permitted to use in 2544. (You are still NOT permitted to use these operators in your code.) Each assign statement that uses the addition or subtraction operator instantiates its own 4-bit adder. For example, lines 8 and 9 alone in the code below will produce two separate 4-bit ripple carry adders. Using the assumptions above, determine the transistor count an propagation delay of this circuit.

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Chapter1: Introduction
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Consider the circuit shown below. Notice that it utilizes dataflow Verilog operators that you are not
permitted to use in 2544. (You are still NOT permitted to use these operators in your code.) Each assign
statement that uses the addition or subtraction operator instantiates its own 4-bit adder. For
example, lines 8 and 9 alone in the code below will produce two separate 4-bit ripple carry adders.
Using the assumptions above, determine the transistor count an propagation delay of this circuit.
// Combinational circuit 2
module comb_ckt_2(S,X,Y,R);
input [3:0] X,Y;
input [2:01 R;
[3:01 s;
output
wire
[3:01 ni, n2, n3, n4, n5, n6, n7;
assign n1X + Y;
assign n2 = X + Y + 1;
assign n3X + ~Y;
assign n4
assign n5 = x;
assign n6 X + 1;
assign n7 X - 1;
assign s
(R
(R
endmodule
X + ~Y + 1;
(R
(R
3'b000) ?
3'b001) ?
(R
(R
3'b010) ?
3'b011) ? n4
3'b100) ? n5
3'b101) ? n6
(R3'b110) ? n7:
(R3'b111) ? 4'h0 4'bxxxx; 22
Transistor count for line 9: [Select]
Transistor count for line 10: [Select]
Transistor count for line 11: [Select]
Transistor count for line 12: [Select]
Transistor count for line 13: [Select]
Transistor count for line 14: [Select]
12345OLOSHIRES-59
Transistor count for lines 15-22: [Select]
11
12
13
14
<
Transistor Count
Determine the transistor count for the circuit produced by each assign statement. (For example, line
8 contains the statement "assign n1 = X+Y;")
Transistor count for line 8:
[Select]
15
16
WN1068NGSAWNH
17
18
19
20
~~~~
21
23
Transcribed Image Text:Consider the circuit shown below. Notice that it utilizes dataflow Verilog operators that you are not permitted to use in 2544. (You are still NOT permitted to use these operators in your code.) Each assign statement that uses the addition or subtraction operator instantiates its own 4-bit adder. For example, lines 8 and 9 alone in the code below will produce two separate 4-bit ripple carry adders. Using the assumptions above, determine the transistor count an propagation delay of this circuit. // Combinational circuit 2 module comb_ckt_2(S,X,Y,R); input [3:0] X,Y; input [2:01 R; [3:01 s; output wire [3:01 ni, n2, n3, n4, n5, n6, n7; assign n1X + Y; assign n2 = X + Y + 1; assign n3X + ~Y; assign n4 assign n5 = x; assign n6 X + 1; assign n7 X - 1; assign s (R (R endmodule X + ~Y + 1; (R (R 3'b000) ? 3'b001) ? (R (R 3'b010) ? 3'b011) ? n4 3'b100) ? n5 3'b101) ? n6 (R3'b110) ? n7: (R3'b111) ? 4'h0 4'bxxxx; 22 Transistor count for line 9: [Select] Transistor count for line 10: [Select] Transistor count for line 11: [Select] Transistor count for line 12: [Select] Transistor count for line 13: [Select] Transistor count for line 14: [Select] 12345OLOSHIRES-59 Transistor count for lines 15-22: [Select] 11 12 13 14 < Transistor Count Determine the transistor count for the circuit produced by each assign statement. (For example, line 8 contains the statement "assign n1 = X+Y;") Transistor count for line 8: [Select] 15 16 WN1068NGSAWNH 17 18 19 20 ~~~~ 21 23
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