Consider a swapping system in which memory consists of the holes as shown in Fig. 4. Note that A to I represent processes in memory, and H₁ to Hg are eight holes. Process P₁, P2, ..., Ps are generated sequentially, and their sizes are as follows: P₁ requests 8 KB. P2 requests 10KB. P3 requests 13KB. P4 requests 5KB V. Ps requests 4KB Answer the following questions: 1. 11. 111. IV. H₁ 4KB A H₂ B H3 10KB 5KB с A/ H4 D 16KB H5 E 8KB H6 G 9KB H7 15KB I Hs 13KB Fig. 4 (1) When using First-Fit algorithm, which hole will P1, P2, P3, P4 and P5 will be loaded into, respectively? Put your answer in the following 5 blanks, from left to right (First blank is for P1, second blank is for P2, ..., 5th blank is for P5), case insensitive. (Chose H1, H2, or H8) (2) When using Best-Fit algorithm, which hole will P1, P2, P3, P4 and P5 will be loaded into, respectively? Put your answer in the following 5 blanks, from left to right (First blank is for P1, second blank is for P2, ..., 5th blank is for P5), case

Consider a swapping system in which memory consists of the holes as shown in Fig. 4. Note that A to I represent processes in memory, and H₁ to Hg are eight holes. Process P₁, P2, ..., Ps are generated sequentially, and their sizes are as follows: P₁ requests 8 KB. P2 requests 10KB. P3 requests 13KB. P4 requests 5KB V. Ps requests 4KB Answer the following questions: 1. 11. 111. IV. H₁ 4KB A H₂ B H3 10KB 5KB с A/ H4 D 16KB H5 E 8KB H6 G 9KB H7 15KB I Hs 13KB Fig. 4 (1) When using First-Fit algorithm, which hole will P1, P2, P3, P4 and P5 will be loaded into, respectively? Put your answer in the following 5 blanks, from left to right (First blank is for P1, second blank is for P2, ..., 5th blank is for P5), case insensitive. (Chose H1, H2, or H8) (2) When using Best-Fit algorithm, which hole will P1, P2, P3, P4 and P5 will be loaded into, respectively? Put your answer in the following 5 blanks, from left to right (First blank is for P1, second blank is for P2, ..., 5th blank is for P5), case

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Consider a swapping system in which memory consists of the holes as shown in Fig.A. Note that A to I represent processes in memory, and Hj to Hg are eight holes. Process Pj, P. ... , Ps are generated sequentially, and their sizes are as follows: i Pi requests 8 KB. P2 requests 10KB. i. 111. P3 requests 13KB. iv. P4 requests 5KB Ps requests 4KB V. Answer the following questions: Н. А На в На с 10KB H4 16KB D Hs 8KB E He G 9KB H: I 15KВ Hs 13KB 4KB 5KB Fig. A (a) When using First-fit algorithm, (1) which hole will P1 will be loaded into? (2) which hole will P5 will be loaded into? (b) When using Best-fit algorithm, (3) which hole will P1 will be loaded into? (4) which hole will P5 will be loaded into? (c) When using worst-fit algorithm, (5) which hole will P1 will be loaded into? (6) which hole will P4 will be loaded into? (7) which hole will P5 will be loaded into? (d) When using Next-fit algorithm, (8) which hole will P2 will be loaded into? (9) which hole will P3 will be loaded into?…
Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?
Create a memory mapping from the cache memory of 512 MB to the main memory of 4 GB using the four-way set associative approach with a block size of 1 MB. Consider that each memory location may be accessed using a byte address.
Suppose a byte-addressable computer using set associative cache has 224 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Consider the free memory layout shown below (the blocks are ordered from top to bottom). To the right, draw to the what the free memory layouts would be after satisfying requests for (in order) memory blocks of size 55K, 210K, 381K, and 395K. Draw one memory layout for the best-fit algorithm, and one for first-fit. 500K 300K 200K 300K
Consider a demand-paging system with a paging disk that has an average access/transfer time of 50 ms. Addresses are translated through a page table in main memory, with an access time of 500 ns per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added a TLB that reduces access time to one memory reference if the page-table entry is in the TLB. Assume that 80% of the accesses are in the TLB and that, of those remaining, 15% (or 3% of the total) cause page faults. We assume that the TLB access time is 20 ns. What is the effective access time?
Consider the following example and perform complete working of paging, generate the logical and physical addresses too. Let us consider the main memory size 16 Kb and Framesize is 2 KB therefore the main memory will be divided into the collection of 8 frames of 2KB each. There are 3 processes in the system that is P1, P2 and P3 of 4 KB each. Each process is divided into pages of 2 KB each so that one page can be stored in one frame. Cpuwants 2nd kb of 3rd process for processing
A cache memory has a line size of eight 64-bit words and a capacity of 4K words. The main memory size that is cacheable is 1024 Mbits. Assuming 4-way set associative mapping and that the addressing is done at the byte level. What is the format of the main memory addresses (i.e s-d, d, and w)? For the hexadecimal main memory location 2BFACEDH, find the corresponding 4-way set-associative memory format
Suppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache? Show all work and explain how you got the answers please. Thanks
Consider a fully-associative cache of size 4. Each slot in the cache can have just one item (i.e. the line size is 1 item). The cache is empty to start with. The cache uses an LRU replacement policy: every slot has a counter; every time a slot is accessed, a global counter is incremented and the value is stored in the slot counter; the slot with the lowest counter value is chosen for replacement. Sequence Id 1 2 3 4 5 6 7 8 10 Address Ox0012 0x0014 Ox0016 Ox0018 0x0016 0x0012 0x0020 Ox0022 0x0014 Ox0012 Hit/Miss Accesses 1 to 10 are respectively: Select one: O a. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Miss O b. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Hit O. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Miss O d. Miss, Miss, Miss, Miss, Hit, Miss, Miss, Miss, Miss, Hit O e. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Hit
In the scenario above, calculate the average time to access a word, given.
The memory access time is I nanosecond for read operation with a hit in cache. * nanoseconds for a read operation with a miss in cache, 2 nanoseconds for a write operation with a hit in cache and 10 anoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves 100 instruction fetch operations, 60 memory operand read operations and 40 memory operand write operations. The cache hit-ratio is 0.9. The average memory access time (in nanoseconds) in executing the sequence of instructions is