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Consider a program having following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers. Instructions requiring floating Unit (FPU) are indicated in the comment field. Please note that LOAD, STORE and FPU operations require 4, 4 and 3 clock cycles respectively whereas integer operations require one clock cycle only. a) Show the execution sequence of the program using in-order-issue and in-order-execution policy.

Consider a program having following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers. Instructions requiring floating Unit (FPU) are indicated in the comment field. Please note that LOAD, STORE and FPU operations require 4, 4 and 3 clock cycles respectively whereas integer operations require one clock cycle only. a) Show the execution sequence of the program using in-order-issue and in-order-execution policy.

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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1. Consider a program having following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers. Instructions requiring floating Point Unit (FPU) are indicated in the comment field. Please note that LOAD, STORE and FPU operations require 4, 4 and 3 clock cycles respectively whereas integer operations require one clock cycle only. a) Show the execution sequence of the program using in-order-issue and in-order-execution policy. Instructions Comment LOAD R2, [R1] ADD R3, R1, R2 STORE [R5], R3 ADD R1, R6, 16H FPU SUB R5, R4, R3 FPU STORE [R2], RS AND R4, R2, 15H OR R3, R1, 25H LOAD R2, M1 SUB R4, R3, R2 FPU STORE M2. R4 System Integer ALU Fetch Write-back Decode Unit-1 Unit-1 Unit-1 Floating Point Unit Decode Unit-2 Fetch Write-back Unit-2 Activate Windov Unit-2 Integer ALU Go to Settings to acti
Transcribed Image Text:1. Consider a program having following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers. Instructions requiring floating Point Unit (FPU) are indicated in the comment field. Please note that LOAD, STORE and FPU operations require 4, 4 and 3 clock cycles respectively whereas integer operations require one clock cycle only. a) Show the execution sequence of the program using in-order-issue and in-order-execution policy. Instructions Comment LOAD R2, [R1] ADD R3, R1, R2 STORE [R5], R3 ADD R1, R6, 16H FPU SUB R5, R4, R3 FPU STORE [R2], RS AND R4, R2, 15H OR R3, R1, 25H LOAD R2, M1 SUB R4, R3, R2 FPU STORE M2. R4 System Integer ALU Fetch Write-back Decode Unit-1 Unit-1 Unit-1 Floating Point Unit Decode Unit-2 Fetch Write-back Unit-2 Activate Windov Unit-2 Integer ALU Go to Settings to acti
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