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Consider a dynamic domino logic circuit shown below. Suppose that each transistor has an internal gate capacitor Cg and drain capacitor CD: CG= CoxW L; Cp= (CoxW L)/2; Cox=0.1 pF/um2. Equivalent resistor for an NMOS transistor: RN=(12kQ) / (W/L)N Equivalent resistor for a PMOS transistor: Rp=(24kQ) / (W/L)P Suppose that all four CMOS inverters are identical with same WN-In and Wp-In Values. WNi=Wn2=WN3=lu_ _Wpi=2u, Wp-h=2u, WN-n=lu, L=lu for all transistors. VIN=|VTP|=1V, VDD=5V. VDD VDD MP1 Mp2 CLK OUT-2 OUT-1 X1 MN3 MNS X2 MN2 CLK MN4 Cascaded Dynamic Circuits a) Derive a Boolean expression ofƒ in terms of x, and x, in evaluation phase. b) Find the value of WNs if VoUT-1=4.5V as a result of charge sharing (problem). c) Find the worst case tpHL for OUT-1. Suppose that all input transitions happen in pre- charge phase and each circuit node has an initial voltage value of either 0V or 5V. d) Find the values of Wp2 and WN4 if the worst case tpHL for OUT-1, calculated in c), is same the clock delay (total delay of two cascaded inverters).

Consider a dynamic domino logic circuit shown below. Suppose that each transistor has an internal gate capacitor Cg and drain capacitor CD: CG= CoxW L; Cp= (CoxW L)/2; Cox=0.1 pF/um2. Equivalent resistor for an NMOS transistor: RN=(12kQ) / (W/L)N Equivalent resistor for a PMOS transistor: Rp=(24kQ) / (W/L)P Suppose that all four CMOS inverters are identical with same WN-In and Wp-In Values. WNi=Wn2=WN3=lu_ _Wpi=2u, Wp-h=2u, WN-n=lu, L=lu for all transistors. VIN=|VTP|=1V, VDD=5V. VDD VDD MP1 Mp2 CLK OUT-2 OUT-1 X1 MN3 MNS X2 MN2 CLK MN4 Cascaded Dynamic Circuits a) Derive a Boolean expression ofƒ in terms of x, and x, in evaluation phase. b) Find the value of WNs if VoUT-1=4.5V as a result of charge sharing (problem). c) Find the worst case tpHL for OUT-1. Suppose that all input transitions happen in pre- charge phase and each circuit node has an initial voltage value of either 0V or 5V. d) Find the values of Wp2 and WN4 if the worst case tpHL for OUT-1, calculated in c), is same the clock delay (total delay of two cascaded inverters).

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
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Consider a dynamic domino logic circuit shown below. Suppose that each transistor has an internal gate capacitor CG and drain capacitor Cp: CG= CoxW L; Cp= (CoxW L)/2; Cox=0.1 pF/um2. Equivalent resistor for an NMOS transistor: RN=(12kQ) / (W/L)N Equivalent resistor for a PMOS transistor: Rp= (24kQ) / (W/L)P Suppose that all four CMOS inverters are identical with same WN-In and WP-In values. WNi=WN2=WN3=lu Wpi=2u, Wp.n=2u, WN-h=lu, L=lu for all transistors, VTN=|VTP|=1V, VDD=5V. VDD VDD MP1 MP2 CLK OUT-2 OUT-1 f MNS X1 MN3 x2 MN2 CLK ► MM MN4 Cascaded Dyamic Circuits a) Derive a Boolean expression of f in terms of x, and x, in evaluation phase. b) Find the value of WN5 if VoUT-1=4.5V as a result of charge sharing (problem). c) Find the worst case tpHL for OUT-1. Suppose that all input transitions happen in charge phase and each circuit node has an initial voltage value of either 0V or 5V. d) Find the values of WP2 and WN4 if the worst case tpHL for OUT-1, calculated in c), is same the clock delay (total delay of two cascaded inverters). pre-
Transcribed Image Text:Consider a dynamic domino logic circuit shown below. Suppose that each transistor has an internal gate capacitor CG and drain capacitor Cp: CG= CoxW L; Cp= (CoxW L)/2; Cox=0.1 pF/um2. Equivalent resistor for an NMOS transistor: RN=(12kQ) / (W/L)N Equivalent resistor for a PMOS transistor: Rp= (24kQ) / (W/L)P Suppose that all four CMOS inverters are identical with same WN-In and WP-In values. WNi=WN2=WN3=lu Wpi=2u, Wp.n=2u, WN-h=lu, L=lu for all transistors, VTN=|VTP|=1V, VDD=5V. VDD VDD MP1 MP2 CLK OUT-2 OUT-1 f MNS X1 MN3 x2 MN2 CLK ► MM MN4 Cascaded Dyamic Circuits a) Derive a Boolean expression of f in terms of x, and x, in evaluation phase. b) Find the value of WN5 if VoUT-1=4.5V as a result of charge sharing (problem). c) Find the worst case tpHL for OUT-1. Suppose that all input transitions happen in charge phase and each circuit node has an initial voltage value of either 0V or 5V. d) Find the values of WP2 and WN4 if the worst case tpHL for OUT-1, calculated in c), is same the clock delay (total delay of two cascaded inverters). pre-
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