Consider a computer with the following characteristics: total of 256Mbyte of main memory; block size of 8 bytes; and cache size of 128 Kbytes. Design a direct-mapping address structure. Design an associative-mapping address structure. iii. Design a two-way set-associative-mapping address structure. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag and offset values for a fully-associative cache. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag, cache set, and word offset values for a two-way set-associative cache.
Consider a computer with the following characteristics: total of 256Mbyte of main memory; block size of 8 bytes; and cache size of 128 Kbytes. Design a direct-mapping address structure. Design an associative-mapping address structure. iii. Design a two-way set-associative-mapping address structure. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag and offset values for a fully-associative cache. For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag, cache set, and word offset values for a two-way set-associative cache.
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Consider a computer with the following characteristics: total of 256Mbyte of main memory; block size of 8 bytes; and cache size of 128 Kbytes.
- Design a direct-mapping address structure.
- Design an associative-mapping address structure.
iii. Design a two-way set-associative-mapping address structure.
- For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag, cache line address, and word offsets for a direct-mapped cache.
- For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag and offset values for a fully-associative cache.
- For the main memory addresses of F0010ABH, F012356H, and 00CABBEH, give the corresponding tag, cache set, and word offset values for a two-way set-associative cache.
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