**Latch Timing Diagram Exercise****Objective:**Complete the timing diagram below for the active-HIGH latch shown. The latch is initially set.**Diagram Explanation:**This illustration features two main components:1. **Timing Diagram (Left Side):** - The diagram consists of four horizontal lines labeled `S`, `R`, `Q`, and `Q̅`. - Each line is divided into segments representing time intervals, marked by vertical grid lines. - Signal transitions are shown as changes in level (either high or low) within each line.2. **Latch Symbol (Right Side):** - A simple block diagram representing a latch with inputs `S` (Set) and `R` (Reset). - Outputs are labeled `Q` and `Q̅` (the inverse of `Q`).**Instructions:**1. Analyze the transitions for inputs `S` and `R`.2. Update the `Q` and `Q̅` lines accordingly based on the active-HIGH behavior of the latch: - If `S` is high and `R` is low, `Q` should be set. - If `R` is high and `S` is low, `Q` should be reset. - If both `S` and `R` are low, maintain the previous state. - If both `S` and `R` are high, consider it an invalid condition for a typical SR latch.The initial state is set, so `Q` starts high and `Q̅` starts low. Adjust the diagram based on these rules to complete the timing analysis.

According to the information given:- We have to follow the information instruction in order to complete the timing diagram.The SR latch output is HIGH when SET (S) is active high. The SR latch output is LOW when RESET (R) is active high. Timing diagram: Because the latch is initially set, the state of the output (Q) before the first active SET or RESET is HIGH. The Q output is HIGH until the RESET function is active high and goes to active LOW when the RESET function is active high (R=1). Now the SET S high pulse function is active again, therefore the output changes state from low to HIGH.