clock pulse and once on the falling edge is called: a) DDR-DRAM b) CDRAM c) RDRAM d) SDRAM

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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4) The version of DRAM, which can send data twice per clock eycle, once on the rising edge of the
clock pulse and once on the falling edge is called:
a) DDR-DRAM
b) CDRAM
c) RDRAM
d) SDRAM
5) In direct mapping cache memory, the Block number 5m-1 is mapping in cache line:
b) m-1
6) In CD-ROM format, when Mode 2, the size of user data is:
c) m
d) m+1
a) 0
a) Data field
b) Data field -
ECC Field
e) Data field +
ECC Field
d) ECC field
7) The IEEE 32-bit floating-point number (0 10000010 10001100000000000000000) represent of:
d) 7.443676776E38
a) 12.375
b) 4.375
c) 2.105497145E39
8) Execute the instruction: BSA X: X is memory location, need:
b) 3 steps and 3
u operations
a) 5 steps and 5
u operations
c) 5 steps and 3
u operations
d) 3 steps and 5
u operations
9) The time of Executing one instruction in 4 stage pipelining is ---- of the time when the instruction
execution in sequational process.
a) twice
b) equal
c) half
d) quarter
10) The registers are involves in Indirect Cycle are:
a) MAR, MBR,
b) MAR, MBR, PC
c) MAR, MBR, IR
d) MAR, MBR
Control unit.
20
Transcribed Image Text:4) The version of DRAM, which can send data twice per clock eycle, once on the rising edge of the clock pulse and once on the falling edge is called: a) DDR-DRAM b) CDRAM c) RDRAM d) SDRAM 5) In direct mapping cache memory, the Block number 5m-1 is mapping in cache line: b) m-1 6) In CD-ROM format, when Mode 2, the size of user data is: c) m d) m+1 a) 0 a) Data field b) Data field - ECC Field e) Data field + ECC Field d) ECC field 7) The IEEE 32-bit floating-point number (0 10000010 10001100000000000000000) represent of: d) 7.443676776E38 a) 12.375 b) 4.375 c) 2.105497145E39 8) Execute the instruction: BSA X: X is memory location, need: b) 3 steps and 3 u operations a) 5 steps and 5 u operations c) 5 steps and 3 u operations d) 3 steps and 5 u operations 9) The time of Executing one instruction in 4 stage pipelining is ---- of the time when the instruction execution in sequational process. a) twice b) equal c) half d) quarter 10) The registers are involves in Indirect Cycle are: a) MAR, MBR, b) MAR, MBR, PC c) MAR, MBR, IR d) MAR, MBR Control unit. 20
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