Caches are important in providing processors with a high-performance memory hierarchy. Below is a list of 32-bit memory address references represented in Hex. 0x00C, 0x2D0, 0x0AC, 0x008, 0x2FC, 0x160, 0x2F8, 0x038, 0x2D4, 0x0B0, 0x2E8, 0x3F4 You are asked to optimize a cache design for the given references. There are three direct- mapped cache designs possible, all with 8 words of data: C1 has 1-word blocks, C2 has 2-word blocks, and C3 has 4-word blocks. In terms of miss rate, which cache design is the best?
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- A memory system has 4 KB byte-addressable main memory and a direct-mapped cache that consists of 8 blocks with 16 bytes per block. The following shows the main memory address format that allows us to map addresses from main memory to cache. Note: 12 bit address, 4 bit offset, 3 bit $block, and 5 bit tag Assume the cache directory shown below:microprocessor 8086. Assume SP=0XE99D, R16=0XE2, R17=0x25, R01=0XFC, R15=0X1F and the following memory information. Address contents (hex) post Address contents (hex) post pre 22 pre 44 OXE996 OXE99C OXE997 46 OXE99D C5 OXE998 17 OXE99E Аб OXE999 21 OXE99F 77 ОхЕ99A F2 OXE9A0 78 OXE99B C3 OXE9A1 A5 Find the values of the registers SP, R01, R16 and R17 after the following operations. РОP R01 РО R16 РОP R17 РOP R20 PUSH R15 SP R16 R17 R01 R20 R15
- Microprocessor Hw Q1 Execute the following code and show the contents of the registers: LDI R16,$03 LDI R17,$10 HERE: AND R16, R17 BREQ HERE ADD R16,17 Q2 Find the number of times the following loop is performed: LDI R20,20 BACK: LDI R21,$0A HERE: DEC R21 BRNE HERE DEC R20 BRNE BACK Q3. Execute the following code and show the contents of the registers: LDI R16,$03 LDI R17,$15 HERE: ADD R16, R17 COM R16 BRSH HERE EOR R16,17 JMP NEXT SUB R16,R17 NEXT: ROR R16In designing a computer’s cache system, the cache block or cache line size is an important parameter. Which of the following statements is correct in this context? A smaller block size implies better spatial locality A smaller block size implies a smaller cache tag and hence lower cache tag overhead A smaller block size implies a larger cache tag and hence lower cache hit time A smaller bock size incurs a lower cache miss penaltyMicroprocessor 8086
- A 2-way set-associative cache consists of four sets. Main memory contains 2K blocks of 8 bytes each and byte addressing is used.Q.) Compute the hit ratio for a program that loops three times from addresses 0x8 to 0x33 in main memory. You may leave the hit ratio in terms of a fraction.Do pleaseintel 8086 microprocessor
- 0001 = Load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory 0011 = Load AC (the accumulator register) from an I/O device 0111 = Store AC to an I/O device With these instructions, a particular I/O device is identified by replacing the 12-bit address portion with a 12-bit device number. Remember that a number ending with a small ‘h’ means the number is a hexadecimal number. What is the hexadecimal string that expresses the following instructions? Load AC from memory location 62h. Add the contents of memory location 451h to AC. Store AC to memory location 8h. Store AC to I/O device number 8h.0001 = Load AC from memory 0010 = Store AC to memory 0101 = Add to AC from memory 0011 = Load AC (the accumulator register) from an I/O device 0111 = Store AC to an I/O device With these instructions, a particular I/O device is identified by replacing the 12-bit address portion with a 12-bit device number. Remember that a number ending with a small ‘h’ means the number is a hexadecimal number. What is the hexadecimal string that expresses the following instructions? Load AC from memory location 62h. Add the contents of memory location 451h to AC. Store AC to memory location 8h. Store AC to I/O device number 8h.Consider the following table that represents part of the memory of a 16-bit address space that has an addressability of 2 bytes (like LC-3): ADDRESS OxFFFF OXOCOE OXOCOD Ox0C0C OXOCOB OXOCOA 0x0C09 0x0000 CONTENTS 1111 1111 1111 1111 1111 1110 1101 1100 0001 1011 1100 0101 0110 0101 1000 0111 1100 0000 0100 0000 0011 0001 0101 0010 0000 1100 0000 1101 0000 0000 0000 0000 The table above shows the addresses in hex (base 16) and the contents at the corresponding address in binary (base 2). A.) What are the contents in hex of the memory location at following address in binary: 0000 1100 0000 1110? (Enter hex like the following example: Ox2A3F)