btain the ruth table for a 2-to-1 word-sized mux where the two input buses and output bus are all 2-bits wide. Use INO_1, INO_1, IN1_0, IN1_1, S for the inputs and OUT_0 and OUT_1 for the outputs. Obtain the schematic diagram for a possible implementation of such a mux following the example given in Figure 3.4.

Database System Concepts
7th Edition
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Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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Construct the word-sized 2-to-1 mux designed in Prelab step 4)

 

4) Obtain the truth table for a 2-to-1 word-sized mux where the two input buses and output bus are
all 2-bits wide. Use INO_1, INO_1, IN1_0, IN1_1, S for the inputs and OUT_0 and OUT_1 for
the outputs. Obtain the schematic diagram for a possible implementation of such a mux following
the example given in Figure 3.4.
Transcribed Image Text:4) Obtain the truth table for a 2-to-1 word-sized mux where the two input buses and output bus are all 2-bits wide. Use INO_1, INO_1, IN1_0, IN1_1, S for the inputs and OUT_0 and OUT_1 for the outputs. Obtain the schematic diagram for a possible implementation of such a mux following the example given in Figure 3.4.
A total of three 2-input AND gates connected as shown in Figure 3.4 would be required to imple-
ment this word-sized AND gate.
MO
ΚΟ
M1
K1
M2
K2
D
D
OUTO
OUT1
OUT2
Figure 3.4: Implementation of the word-sized AND gate.
Transcribed Image Text:A total of three 2-input AND gates connected as shown in Figure 3.4 would be required to imple- ment this word-sized AND gate. MO ΚΟ M1 K1 M2 K2 D D OUTO OUT1 OUT2 Figure 3.4: Implementation of the word-sized AND gate.
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