Based on the following circuits, find values read at state Q at the time i Q & R S Time i S 1 R 0 Qn+1 0 1 0 0 2 0 1 3 0 0 4 1 0 0 0 6 0 1 7 0 0 8 1 0 9 0 10

g Boolean Function: F(w,x,y,z) = (8,10,12,14)

code your Boolean function in HDL And.hdl: /** * And gate: * out = 1 if (a == 1 and b == 1) * 0 otherwise */ CHIP And { IN a, b; OUT out; PARTS: Nand(a=a, b=b, out=nandAB); Not(in=nandAB, out=out); } Mystery.hdl CHIP Mystery { IN a, b, c, d; OUT out; PARTS: } Not.hdl /** * Not gate: * out = not in */ CHIP Not { IN in; OUT out; PARTS: // Put your code here: Nand(a=in, b=in, out=out); } Or.hdl /** * Or gate: out = 1 if {a==1 or b==1}, 0 otherwise */ CHIP Or { IN a, b; OUT out; PARTS: Not (in=a, out=nota); Not (in=b, out=notb); Nand (a=nota, b=notb, out=out); }

Task 4: Application of 7-Segment Display Controller: You are to design a combinational circuit that displays the 7-segment display outputs triggered by the following 2 input combinations. The block diagram of the required design is shown below. Combinational Circuit a) Complete the table below. Inputs Y 7-segments Output (small letter) a e 1 b) Plot the truth table entries in the K-map matrix and simplify. Y X X a = b = C= Y Y X X X d = e = f = g = c) Draw and build the combinational logic circuit below.

Computer Engineering Subject name DLD . Code PS15 Task 3.1 Implementation of Combination Logic Circuit using PLA Like ROM, PLA can be mask-programmable or field-programmable. With a mask-programmable PLA, the user must submit a PLA program table to the manufacturer. This table is used by the vendor to produce a user-made PLA that has the required internal paths between inputs and outputs. A second type of PLA available is called a field-programmable logic array or FPLA. The FPLA can be programmed by the user by means of certain recommended procedures. FPLAs can be programmed with commercially available programmer units. ,As mentioned earlier, user has to submit PLA program table to the manufacturers to get the user-made PLA. Let the students to try how to determine PLA program table with the help of a question.Draw a PLA circuit to implement the logic functions A'BC + AB'C + AC' and A'B'C' + BC.

Complete the truth table for the XOR gate: X⊕Y DO QUESTION 7. X Y X ⊕ Y 0 0   0 1   1 0   1 1     2. What is the algebraic expression for XOR? (hint: create from the truth table) Sum of products form:   Product of sums form:   3. Build the truth table for this function: F(A,B,C) = B’(A⊕C’) + BC +A’C   4. Draw the circuit diagram that represents this equation. How many gates are used in the diagram?   5. Using Boolean algebra, eliminate the exclusive OR gate, then factor to obtain a minimum product of sums.   6. Verify this second equation with a truth table. (Does it match step 3?)   7. Make a second circuit diagram to represent the new minimized equation. How many gates are found in the second circuit?   8. Implement the two circuits on the breadboards. (From steps 4 and 7.)

Question 8: Draw the circuit that implements each of the following equations: B + AC' (W + Y)' + X' (B + A'D) + (BC)' (W' + XY)' + (VWX' + Z)'

Please help with all parts

subjejct :digital logic solve only if you had knowledge

Draw the circuit diagram that implements the expression ABC(A+D)