b) Now assume you have a 2 bit full adder/subtractor, put this together with AND/OR ga to build a simple ALU. You may assume that the adder/subtractor can correctly outpu the carry bit. Now design and build a simple ALU that has following functions on 2-bit binary inputs A and • AND • OR Add Less Than • Arithmetic Right Shift The following outputs are required: • Result • Negative: A bit indicates whether the result is negative or not • Zero: A bit indicates whether the result is zero or not • Carry You are also given four 2:1 muxes and you may assume that the Add unit can correct output carry bits.
b) Now assume you have a 2 bit full adder/subtractor, put this together with AND/OR ga to build a simple ALU. You may assume that the adder/subtractor can correctly outpu the carry bit. Now design and build a simple ALU that has following functions on 2-bit binary inputs A and • AND • OR Add Less Than • Arithmetic Right Shift The following outputs are required: • Result • Negative: A bit indicates whether the result is negative or not • Zero: A bit indicates whether the result is zero or not • Carry You are also given four 2:1 muxes and you may assume that the Add unit can correct output carry bits.
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Need help with PART B
Transcribed Image Text:b) Now assume you have a 2 bit full adder/subtractor, put this together with AND/OR gates
to build a simple ALU. You may assume that the adder/subtractor can correctly output
the carry bit.
Now design and build a simple ALU that has following functions on 2-bit binary inputs A and B:
• AND
• OR
• Add
• Less Than
• Arithmetic Right Shift
The following outputs are required:
• Result
• Negative: A bit indicates whether the result is negative or not
• Zero: A bit indicates whether the result is zero or not
• Carry
You are also given four 2:1 muxes and you may assume that the Add unit can correctly
output carry bits.
Transcribed Image Text:Q3. Logical Operation and ALU
a) Design a 2-bit bitwise subtractor given 2 XOR gates, 2 full adders and an input signal
C_in.
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