b) Design a PLL circuit (Find R1 and C2) shown below for fo = 12kHz and f = 60HZ and assume C = 10nF. -Vcc=+10 V C3 0.001 uF R1 10 Input Demodulated 2 output Reference 6. output NE/SE-565 VCO output 4. 3 5 6 VEE =-10 V

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b) Design a PLL circuit (Find R1 and C2) shown below for f. = 12kHz and fe = 60HZ and assume C1 = 10nF.
-Vcc=+10 V
C2
R1
0.001 µF
10
Input
Demodulated
output
Reference
6.
output
NE/SE-565
VCO output
4
3
5
9
1
C
VEE =-10 V
Transcribed Image Text:b) Design a PLL circuit (Find R1 and C2) shown below for f. = 12kHz and fe = 60HZ and assume C1 = 10nF. -Vcc=+10 V C2 R1 0.001 µF 10 Input Demodulated output Reference 6. output NE/SE-565 VCO output 4 3 5 9 1 C VEE =-10 V
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