(b) Consider an ARM CPU that executes its instructions using a simple 3-stage pipeline consisting of fetch, decode, and execute stages. Show how the instructions in the following ARM code would pass through the pipeline by copying and completing the table below for the first nine cycles only. The first three lines have been completed for you. You should highlight in your table where any structural hazards and control hazards occur. : string length routine : Input: : Output: RO contains num characters in string strlen RO points to string MOV R2, #0 B strlen_cond strlen_loop ADD R2, R2, #1 ADD RO, RO, #1 strlen_cond LDRB R1, [RO] CMP R1, #0 ENE strlen_loop MOV RO, R2 MOV PC, R14 Сycle Fetch Decode Execute MOV R2, #0 B strlen_cond ADD R2, R2, #1 2 MOV R2, #0 B strlen_cond 3 MOV R2, #0 4 9
(b) Consider an ARM CPU that executes its instructions using a simple 3-stage pipeline consisting of fetch, decode, and execute stages. Show how the instructions in the following ARM code would pass through the pipeline by copying and completing the table below for the first nine cycles only. The first three lines have been completed for you. You should highlight in your table where any structural hazards and control hazards occur. : string length routine : Input: : Output: RO contains num characters in string strlen RO points to string MOV R2, #0 B strlen_cond strlen_loop ADD R2, R2, #1 ADD RO, RO, #1 strlen_cond LDRB R1, [RO] CMP R1, #0 ENE strlen_loop MOV RO, R2 MOV PC, R14 Сycle Fetch Decode Execute MOV R2, #0 B strlen_cond ADD R2, R2, #1 2 MOV R2, #0 B strlen_cond 3 MOV R2, #0 4 9
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question
![(b) Consider an ARM CPU that executes its instructions using a simple 3-stage
pipeline consisting of fetch, decode, and execute stages.
Show how the instructions in the following ARM code would pass through the
pipeline by copying and completing the table below for the first nine cycles
only. The first three lines havé been completed for you. You should highlight in
your table where any structural hazards and control hazards occur.
: string length routine
: Input:
: Output: RO contains num characters in string
strlen
RO points to string
MOV R2, #0
B strlen_cond
strlen_loop
ADD R2, R2, #1
ADD RO, RO, #1
strlen_cond
LDRB R1, [R0]
CMP R1, 10
ENE strlen_loop
MOV RO, R2
MOV PC, R14
Сycle
Fetch
Decode
Execute
MOV R2, #0
B strlen_cond
2
MOV R2, #0
ADD R2, R2, #1
B strlen_cond
MOV R2, #0
4
6.
8](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F725de9f8-8668-478f-ac7d-4cfcbfb57f76%2Fe08fd832-1e1d-4b68-9fc4-c9fdbf3a2b20%2F10yew6s_processed.png&w=3840&q=75)
Transcribed Image Text:(b) Consider an ARM CPU that executes its instructions using a simple 3-stage
pipeline consisting of fetch, decode, and execute stages.
Show how the instructions in the following ARM code would pass through the
pipeline by copying and completing the table below for the first nine cycles
only. The first three lines havé been completed for you. You should highlight in
your table where any structural hazards and control hazards occur.
: string length routine
: Input:
: Output: RO contains num characters in string
strlen
RO points to string
MOV R2, #0
B strlen_cond
strlen_loop
ADD R2, R2, #1
ADD RO, RO, #1
strlen_cond
LDRB R1, [R0]
CMP R1, 10
ENE strlen_loop
MOV RO, R2
MOV PC, R14
Сycle
Fetch
Decode
Execute
MOV R2, #0
B strlen_cond
2
MOV R2, #0
ADD R2, R2, #1
B strlen_cond
MOV R2, #0
4
6.
8
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